Evaluation of Radiation Effects in Flash Memories Tetsuo Miyahira ...

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III. NAND and NOR architecture The diagram entitled “NAND and NOR Architecture” contrasts the basic cell structure of both the Samsung NAND and the Intel NOR flash memories. The cell structure is very similar to a MOS transistor except for the floating gate. By adding or removing charge on this floating gate one can turn on or off the transistor. A positive charge on the floating gate relative to the source turns on the device and a negative charge turns it off. Because the floating gate is electrically isolated, it retains its charge indefinitely and hence the cell’s non-volatility. For both the Intel and Samsung devices, erasing is done by the mechanism of Fowler-Nordheim tunneling. For both device types, the control gate is grounded. In the case of the Samsung device, programming voltage is applied to the substrate, but for the Intel device, programming voltage is applied to the source. The electric field generated causes electrons to tunnel away from the floating gate making it more positive and turning the transistor on. Samsung devices also use a form of tunneling for writing of individual floating gates. For writing, the P-well and the N-Substrate are grounded and programming voltage is applied to the control gate. The voltage on the control gate is capacitively coupled to the floating gate, which creates an electric field that causes electrons to tunnel from the P-well to the floating gate making it more negative turning off the transistor. For Intel devices, Channel Hot Electron (CHE) injection is used to program individual transistors. For this approach the source is grounded; the control gate has programming voltage (Vpp) applied to it while the drain gets approximately half of the programming voltage applied to it. The voltage on the control gate is capacitively coupled to the floating gate. This turns the transistor on and causes the current (electrons) to flow from the source to drain. Some of these electrons will have sufficient energy (~3.1eV) to pass through the oxide charging the floating gate. Electrons deposited on the floating gate charge the gate negatively and turns off the transistor. Both manufacturers use charge pumps to get the higher voltages required to program (erase and write) the memory cells. As mentioned earlier, the charge pump is sensitive to radiation damage. The Intel 28F016 devices allow programming to be done with or without the charge pump. In the latter case, programming voltage is applied using an external supply. This flexibility allowed us to evaluate the radiation tolerance of the charge pump by contrasting both options: using the charge pump and bypassing the charge pump. Unfortunately, Intel has 2 eliminated the option of externally supplying programming power in its higher density (32 Mb or greater) parts. As in any MOS device, trapped charge in the oxide will cause a shift in the threshold voltage. The trapped charge from erase and write operations limits the number of erase/write operations allowable by these devices. The additional effect of trapped charges from ionizing radiation will also cause the device to fail. To date there is little data on the combined effect of the two failure mechanisms. The NAND architecture typically uses eight or sixteen cells that are stacked in series with a common bit line. While this arrangement allows for a more compact design, it does cause the device to be more sensitive to radiation damage since radiation-induced leakage will add together. IV. TID RESULTS TID failure of Intel and Samsung flash memories The data displayed in chart entitled “Total Dose Failure Levels” is the result of testing on six test devices from the two manufacturers. The devices were irradiated with Co 60 at room temperature at a rate of 25 rads/sec. The devices were statically biased with both Vpp and Vdd at 5V. As this graph indicates, the Intel NOR flash memory did not fail until 100 krad(Si) when tested bypassing the internal charge pump. An external supply was used to supply programming voltage for this mode. However when the Intel device was tested using the internal charge pump, they failed at ~24 krads. The Samsung NAND flash memory which had no provision for bypassing the charge pump failed at ~10 krads. Based on the results from the Intel tests, with and without the charge pump, it is clear that the charge pump has a significant effect on radiation hardness. The data also suggest that the NAND architecture is more susceptible to TID damage than the NOR architecture. Time to erase using internal charge pump vs. using external supply The plot entitled “Time Required to Erase only” includes data from Intel devices because Samsung devices had no provisions for bypassing the charge pump. When the Intel flash memories were tested with the charge pump bypassed, the data showed no degradation in erase time up to 30 krad(Si). When the internal charge pump was used, the time to erase increased from 30 seconds at pre-
irradiation to 143 seconds at 12 krads for the worst of the six test devices. Supply current (Idd) degradation In the plot entitled “Supply Current (Idd)” shows that Idd for the Samsung device began to rise rapidly at about 8 krads and the device failed functionally at about ~10 krads. Idd for the Intel device began to rise rapidly at about 20 krads and the device failed functionally at ~24 krads. V. SEU RESULTS SEU Tests Unpowered mode. The purpose of this test was to determine if the floating gate would upset with heavy ions. Flash memories use an embedded microcontroller to improve erase/write times. The device was left unpowered, during irradiation, to prevent upsets in the microcontroller, which in turn could cause an upsets in the memory cells. The memory was loaded with a known pattern prior to the test and left unpowered while being irradiated with heavy ions. After the irradiation, the device was powered and tested to see if there were any changes to the pattern. No cell upset occurred when tested in this mode even up to an effective LET of 120 MeV-cm 2 /mg. Static mode. For this mode, the flash memory was powered but there was no active addressing taking place during irradiation. Most of the testing was done using this mode. Before the irradiation, the device was loaded with a known pattern and at the completion of the irradiation, the device was tested to see if the memory content had changed. When testing in this mode, functional interrupts (SEFIs) would occur that in most cases required power cycling (turning Vdd off and then on again) to clear the error condition. We were able to identify seven error modes (lockup conditions). Besides the seven error modes, three Intel devices had catastrophic high current condition that occurred during functionality test after the irradiation was completed. We did not experience this catastrophic high current condition with the Samsung memories. We had no visibility of functionality during irradiation, because we were not addressing the test device when tested in the static mode. Each irradiation run therefore became a pass or fail test. In order to determine a cross section, we selected fluence so that some of the runs resulted in a SEFI and some did not. Cross section was determined by adding the number of SEFIs then dividing by the total fluence (passes as well as fails). The plot of 3 the cross section as a function of LET for the Intel 28F016SV is shown on the graph entitled “Cross Section for Complex Functional Upset Modes.” The error bars are large because we did not know at what point during the irradiation the SEFI occurred or if more than one SEFI occurred during that run. Read mode and erase/write mode. Most of the time was spent testing in the static mode. The results from tests in read and erase/write modes were too limited to include in this paper. We will address these modes further in future tests. Isolating the memory array We used a copper shield to mask off the microcontroller. The diagram entitled “Chip Micrograph” shows the area that was masked from the heavy ions. This was done to see if memory upsets would still occur. We got mixed results from this test, possibly because the sensing and high voltage circuitry was interspersed with the memory array, and could not be masked. With the Intel 28F016SA memories, we observed no errors. The 28F016SV (smart voltage) devices, however, did appear to exhibit memory errors at very high LET. However, the cross section was very low, and it is likely that the apparent memory errors are caused by the response of the more complex SV microcontroller. According to the manufacturer, the SV and SA memory cell technologies are identical and should have behaved similarly. VI. PLAN FOR FOLLOW ON TESTS X2000 Project X2000 Project is driving the flash memory survey. There are currently five missions proposed for X2000 project (Europa, Pluto, Solar Probe, Champollion, and a Mars mission). The Radiation Effects Group at JPL is primarily concerned with the Europa spacecraft because of its severe radiation environment. The Europa spacecraft is expected to be exposed to mostly electron dose of about four megarad(Si), behind 100 mils of aluminum. Design trade studies indicate that it is possible to shield to about 40 krad(Si) in order to gain the advantages of using commercial flash and /or DRAMS as opposed to using an all radiation hardened SRAM. If we are able to find a suitable flash memory, the X2000 modular architecture needs at least one giga-bit and would like eight giga-bits of flash memory for each spacecraft. The follow-on flash memory evaluation will be done in three steps, as described below. Single Event Latchup (SEL) test and cursory Single Event Upset (SEU) tests
Page 1: I. INTRODUCTION Evaluation of Radia
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Evaluation of Radiation Effects in Flash Memories Tetsuo Miyahira ...

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