The first test is planned for first quarter <strong>of</strong> FY99. (October/November time frame). We are <strong>in</strong> the process <strong>of</strong> purchas<strong>in</strong>g flash memories from several manufacturers, <strong>in</strong>clud<strong>in</strong>g denser Samsung and Intel devices (32 Mb or larger). The Intel devices to be tested are a new multi-level technology where each transistor stores two bits. TID test on most <strong>of</strong> the devices We plan to test all <strong>of</strong> the devices that were tested for latchup, unless the SEL data shows a significant reason to omit the device from the test matrix Detailed SEU evaluation We plan to select two devices based on the SEL and TID test results and perform a detailed SEU evaluation us<strong>in</strong>g a new test system currently <strong>in</strong> development. A new test system currently be<strong>in</strong>g developed will be capable <strong>of</strong> captur<strong>in</strong>g detailed <strong>in</strong>formation on each upset and/or SEFI under s<strong>of</strong>tware control. New PCI-based test system The new test system is much faster than the current system and will allow one to scan through the memory more quickly and therefore provide a more complete SEU evaluation. The new system is based on the 33 MHz, 32bit PCI bus <strong>in</strong>stead <strong>of</strong> the 8 MHz, 16-bit ISA bus, which the current system uses. It is expected that an order <strong>of</strong> magnitude <strong>in</strong>crease <strong>in</strong> performance will be ga<strong>in</strong>ed. VII. Conclusions TID conclusions • NOR architecture is <strong>in</strong>herently more robust. • Internal charge pump is particularly susceptible. • Parameters most sensitive to damage are erase/write time. • When the charge pump is bypassed the operat<strong>in</strong>g current is the most sensitive parameter. SEL conclusions • There are enough commercial manufacturers that some will have SEL immunity. SEU conclusions • The memory cells are robust. • “Smarter” control logic <strong>in</strong>creases SEU error modes and susceptibility. • With the exception <strong>of</strong> the catastrophic high current condition that occurred only with the Intel devices, 4 devices from both manufacturers had similar SEU results. Unfortunately COTS is driv<strong>in</strong>g the market towards more radiation sensitivity. • External program supply option is be<strong>in</strong>g elim<strong>in</strong>ated. • Inherently more sensitive NAND architecture is be<strong>in</strong>g used by more manufacturers. • Control logic is becom<strong>in</strong>g “smarter” add<strong>in</strong>g more registers and, thus, SEU susceptibility. VIII. Acknowledgements Significant efforts and contributions to this paper by other (past and present) members <strong>of</strong> JPL’s <strong>Radiation</strong> <strong>Effects</strong> Group are gratefully acknowledged: Larry Edmonds, Steve Guert<strong>in</strong>, Allan Johnston, Choon Lee, Don Nichols, Duc Nguyen, Michael O’Connor, Bernie Rax, Luis Selva, Harvey Schwartz, and Mike Wiedeman. IX. References [1] D. N. Nguyen, C. I. Lee, and A. H. Johnston, “Total Ioniz<strong>in</strong>g Dose <strong>Effects</strong> on <strong>Flash</strong> <strong>Memories</strong>,” 1998 IEEE <strong>Radiation</strong> <strong>Effects</strong> Data Workshop, p. 100. [2] H. R. Schwartz and D. K. Nichols, “S<strong>in</strong>gle-Event Upset <strong>in</strong> <strong>Flash</strong> <strong>Memories</strong>,” IEEE Transactions on Nuclear Science, Vol. 44, p. 2315.
NAND and NOR Architectures 5
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