MB96340 SERIES - Microcontrollers - Fujitsu

Fujitsu Microelectronics Europe
Functional Limitation Report
CI-300035-E-V10
16-BIT MICROCONTROLLER
MB96340 SERIES
FUNCTIONAL LIMITATION 16FXFL0047
DATA FLASH WRITE COMMAND
SEQUENCER
2009-03-16

Revision History
Revision History
Date Issue
2009-03-16 V1.0, Initial Version
This document contains 8 pages.
Abbreviations:
FME Fujitsu Microelectronics Europe GmbH
MCU Microcontroller

Contents
Contents
REVISION HISTORY............................................................................................................ 2
CONTENTS .......................................................................................................................... 3
1 PROBLEM DESCRIPTION .............................................................................................. 5
2 PROBLEM CONDITIONS ................................................................................................ 5
3 AFFECTED DEVICES...................................................................................................... 5
4 ROOT CAUSE ................................................................................................................. 6
4.1 Normal function ....................................................................................................... 6
4.2 Wrong behaviour..................................................................................................... 6
5 WORKAROUND .............................................................................................................. 7
5.1 Direct Flash access (read/write) without write command sequencer........................ 7
5.2 Writing to the Flash with write command sequencer................................................ 7
6 CORRECTIVE ACTION BY FUJITSU.............................................................................. 8

Contents
Fujitsu does not bear any warranty in the case this handling note is not fully
observed.

1 Problem Description
Chapter 1 Problem Description
A problem was found in the Data Flash interface on some 16bit MCUs. The problem does
not occur if the write command sequencer for the Data Flash is disabled. Part numbers are
listed below. This problem is called ‘Data Flash write command sequencer Problem’.
2 Problem Conditions
Problem may occur if all of the following conditions are met:
• Data is written to the Data Flash by using the “Flash write command sequencer”
• The WERINT flag/interrupt function is used or Words are programmed
• A setting for DFCSA:TMG[2:0] is selected which is not valid for command sequencer
writing at the current CLKB frequency (according to Table 2 below)
3 Affected Devices
The following devices are affected:
• MB96F345DSA/ MB96F345DWA/MB96F345FSA/MB96F345FWA/ (all date codes)

4 Root Cause
4.1 Normal function
Chapter 4 Root Cause
The Data Flash interface includes a “write command sequencer” which automatically
submits the command sequence for Flash writing and which checks the progress of the
Flash write operation. Status flags and interrupts inform the CPU or DMA if writing has
terminated successfully or with an error.
The write command sequencer identifies the termination of a write command by waiting for
DFCSA:RDY=1. Afterwards the write command sequencer performs a read access to the
programmed address to verify if the correct data was written to the Flash (“program verify
access”)
If the read data differs from the written data, then the DFWSA:WERINT write error flag will
be set. If such a write error occurs at writing the first byte of a Word, then writing the second
byte will be cancelled.
The write command sequencer is performing read and write accesses with the timing
defined by the DFCSA:TMG[2:0] bits. For each timing setting, a certain maximum CLKB
frequency is defined in the HWM:
Table 1: Definition of Data Flash timing bits according to Hardware manual
4.2 Wrong behaviour
At the “program verify access”, the write command sequencer samples the output data from
the Flash one clock cycle too early. If the CLKB clock frequency is relatively high compared
to the maximum permitted CLKB frequency stated in the table above, then wrong data can
be sampled.
In such a case, the DFWSA:WERINT flag will wrongly be set and can cause an error
interrupt. If this happens at writing the first byte of a Word, then the second byte will not be
written at all.
The following chapters describes up to which CLKB frequency the write command
sequencer is able to correctly perform the “program verify access”.

5 Workaround
Chapter 5 Workaround
5.1 Direct Flash access (read/write) without write command sequencer
There is no limitation when reading the Flash by CPU or DMA or when writing to the Flash
without the write command sequencer (DFWCA:WE=0).
5.2 Writing to the Flash with write command sequencer
Before writing to the Flash with the write command sequencer, the DFCSA:TMG[2:0] bits
must be set according to the following table:
Table 2: Maximum permitted frequencies for writing with command sequencer
TMG2 TMG1 TMG0
Max CLKB frequency
for writing with write
command sequencer
Max CLKB frequency for
reading or for writing without
write command sequencer
(as in Hardware manual)
CLKB
wait
cycles
(read)
0 0 0 3 MHz 7.5 MHz 2 2
0 0 1 6 MHz 16 MHz 3 2
0 1 0 13 MHz 33 MHz 4 2
0 1 1 20 MHz 50 MHz 5 2
1 0 0 33 MHz 66 MHz 7 3
1 0 1 40 MHz 83 MHz 8 4
1 1 0 46 MHz 100 MHz 9 5
1 1 1 100 MHz 100 MHz 10 5
After termination of the write command, the DFCSA:TMG[2:0] bits can be switched back to a
setting with less wait cycles if the smaller number of wait cycles are required for performance
reasons.
CLKB
wait
cycles
(write)

6 Corrective action by Fujitsu
Chapter 6 Corrective action by Fujitsu
Fujitsu will correct this problem by a redesign of the Data Flash write command sequencer
New part numbers are as follows:
• MB96FxxxxxA MB96FxxxxxB
Redesigns are scheduled as follows:
• MB96F345
o ES: 10th June 2009 (shipment)
o CS: 4th Sept 2009 (shipment)