Reconfigurable systems in terms of computer architectures

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Future: The prototype = product Trade-off between HW/SW trade-off: Processor and reconfigurable fabric Granularity issue: fine grain processing ILP, or Task level bit oriented – word oriented distributed on chip memory Large number of architectural choices: Which is ‘the right one’ for a particular application domain? MPSOC 2003, 7-11 July, Chamonix, France, K. Vissers 2-6
Problem definition Perform processing on a stream of data Sampling rates in the order of 100KHz to 100MHz per sample 1000 – 100,000 operations Perform 10 10- 10 11 operations/sec, like add, multiply etc. Take a 200MHz Alu, still need 50-500 of them, Solution: Time multiplex and multi-processor Note: performance is a required part of the solution! MPSOC 2003, 7-11 July, Chamonix, France, K. Vissers 2-7
Page 1 and 2: Reconfigurable Systems in terms of
Page 3 and 4: Overview Introduction Video Signa
Page 5: Theo Claasen: keynote Dac2000 Rapid
Page 9 and 10: What are the solution options Concu
Page 11 and 12: Why can we program processors? Mode
Page 13 and 14: Architecture Design: Y - Chart Benc
Page 15 and 16: Multi-processors Multiple instruct
Page 17 and 18: inputs Exampe VSP architecture, 12-
Page 19 and 20: Example programming VSP with SFG li
Page 21 and 22: Chameleon Second generation Networ
Page 23 and 24: Tile Architecture 16 DPUs with ful
Page 25 and 26: DPU datapath Architecture (conceptu
Page 27 and 28: Simulink based design entry systems
Page 29 and 30: Reconfigurable programming challeng
Page 31 and 32: Recommendation: Kahn Process Networ
Page 33 and 34: Mapping Kahn Process Networks Solve
Page 35 and 36: Programming Reconfigurable Systems
Page 37 and 38: Summary Reconfigurable computing h
Page 39: Selected References J. Henkel, W.

Reconfigurable systems in terms of computer architectures

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