Reconfigurable systems in terms of computer architectures

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Revisit processor architectures Single Risc like processor ILP processing: VLIW for DSP, superscalar for general purpose Very successful programming environment: compilers and OS. Multi processor: no clear winning model, suggested to move to chapter 11 in Computer Architecture, a quantitative approach from Hennessy and Patterson Vector processing MPSOC 2003, 7-11 July, Chamonix, France, K. Vissers 2-8
What are the solution options Concurrently execute 50- 500 operations every clock cycle. Multiple Risc cores, e.g. ARM, MIPS etc. Multiple VLIW oriented DSPs, e.g TI, Starcore etc Build a bit oriented FPGA and synthesize everything on top of that, including processors cores, packet routing networks etc. Build a fabric of interconnected ALUs (coarse grained FPGA) SoC platforms exploiting the best part for the specific application (part). MPSOC 2003, 7-11 July, Chamonix, France, K. Vissers 2-9
Page 1 and 2: Reconfigurable Systems in terms of
Page 3 and 4: Overview Introduction Video Signa
Page 5 and 6: Theo Claasen: keynote Dac2000 Rapid
Page 7: Problem definition Perform process
Page 11 and 12: Why can we program processors? Mode
Page 13 and 14: Architecture Design: Y - Chart Benc
Page 15 and 16: Multi-processors Multiple instruct
Page 17 and 18: inputs Exampe VSP architecture, 12-
Page 19 and 20: Example programming VSP with SFG li
Page 21 and 22: Chameleon Second generation Networ
Page 23 and 24: Tile Architecture 16 DPUs with ful
Page 25 and 26: DPU datapath Architecture (conceptu
Page 27 and 28: Simulink based design entry systems
Page 29 and 30: Reconfigurable programming challeng
Page 31 and 32: Recommendation: Kahn Process Networ
Page 33 and 34: Mapping Kahn Process Networks Solve
Page 35 and 36: Programming Reconfigurable Systems
Page 37 and 38: Summary Reconfigurable computing h
Page 39: Selected References J. Henkel, W.

Reconfigurable systems in terms of computer architectures

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