NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
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<strong>NTUEE</strong> <strong>DSP</strong>/<strong>IC</strong> <strong>Design</strong> <strong>Lab</strong> <strong>Liang</strong>-<strong>Gee</strong> <strong>Chen</strong><br />
<strong>DSP</strong><br />
Control Processor<br />
RISC, CISC<br />
Complexity<br />
Implications of 3G<br />
Memory:<br />
SRAM,<br />
DRAM,<br />
FLASH,<br />
Cache<br />
ROM<br />
● 10-100x higher data rates<br />
● Multimode operation<br />
Technologies<br />
Cost<br />
Configurable<br />
&<br />
programmable<br />
Modules and<br />
Logic<br />
● SoC - CMOS frequency ~ 500 MHz<br />
● <strong>DSP</strong>/µC, RISC + reconfigurable HW<br />
● at “GSM level”<br />
Time to market<br />
● 2 x faster than GSM<br />
mixed signal RF<br />
=> need for totally new design<br />
flows to support Wireless<br />
<strong>Design</strong> Platform concepts<br />
=> assisted generation of HW & SW<br />
from high level descriptions<br />
will be a key enabler for this<br />
capability
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