NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
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<strong>NTUEE</strong> <strong>DSP</strong>/<strong>IC</strong> <strong>Design</strong> <strong>Lab</strong> <strong>Liang</strong>-<strong>Gee</strong> <strong>Chen</strong><br />
System Level <strong>Design</strong>: Driving<br />
Complexity<br />
Forces<br />
What worked at 50K gates won’t<br />
work at 500K<br />
Integration<br />
HW & SW must be co-designed<br />
and co-verified<br />
The system is the chip...drives<br />
full-system simulation!<br />
Application knowledge is critical<br />
Quality Reliability, Risk<br />
Higher volumes, faster ramps & quality expectations mean<br />
higher risk<br />
Time to Market<br />
The right product in minimum time
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