NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
NTUEE DSP/IC Design Lab Liang-Gee Chen
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
<strong>NTUEE</strong> <strong>DSP</strong>/<strong>IC</strong> <strong>Design</strong> <strong>Lab</strong> <strong>Liang</strong>-<strong>Gee</strong> <strong>Chen</strong><br />
<strong>Design</strong> Challenges<br />
Interoperability and integration<br />
SOC designers can’t touch the glue logic like in board design<br />
virtual components may come from several forms<br />
System-level Integration<br />
various languages<br />
embedded processors<br />
develop the software for an as-yet-implemented hardware<br />
Block-to-block interface<br />
various on-chip buses<br />
EDA tool interoperability<br />
data format standards for complex design flow<br />
Testing an SOC<br />
it’s necessary to test each VC separately as well as the entire integrated chip.<br />
Bist, DFT, partial scan, full scan,…<br />
Process-level portability<br />
porting a hard VC from one implementation to another<br />
version control
Change language