NTUEE DSP/IC Design Lab Liang-Gee Chen

System on Chip Design Environment, 

Methodology and Application 

Liang-Gee Chen 

National Taiwan University

NTUEE DSP/IC Design Lab Liang-Gee Chen 

Introduction 

Motivation 

Overview 

Technology & Application Driving 

Design Challenges 

Design Methodologies 

IP-related Issues 

Design Cases 

Conclusions


Introduction 

What are the world wide events? 

FDL’99, IP’99, ….. 

Aug. 24-26, Joint workshop on Challenge 

and Opportunities in Giga-Scale Integration 

for SOC 

Aug. 31--Sept. 1, HDL Workshop 

Sept. 1-- Sept. 2, Workshop on Virtual 

Component Design & Reuse 

Sept. 2-- Sept. 3, Workshop on System 

Specification & Design Language


Moore’s Law


Expectation By SRC Roadmap


Designer’s Challenge

NTUEE DSP/IC Design Lab Liang-Gee Chen


Productivity Gap


Technology Heading of ….


Technology Heading 

Design Details (< 0.25 micron) 

millions of gates in mobile multimedia appliances


Where is Transistor go? 

-- 100 M gates/chip at 2005 

Reconfigurable Interconnections 

! "


“Golden Age” of Electronics


Mobile Multimedia Systems 

on Silicon


Key Challenges for 3G 

3G wireless standards 

Wireless 

create design platform to support standards compliant product 

design 

enable flexible mapping to HW and SW 

migrate existing 2G wireless IP to 3G design platform 

3G wireless appliances 

combine communication and computer capabilities 

integrate, verify and re-use IP from different sources 

3G market segmentation 

allow tighter integration of terminal manufacturers and chip 

manufacturers design flows


The Complexity of 3G/3C Products 

MULTIMEDIA 

COMPUTING 

2005 

bandwidth 

BROADBAND 

complexity 

1995 

1985 

power 

MOBILE


DSP 

Control Processor 

RISC, CISC 

Complexity 

Implications of 3G 

Memory: 

SRAM, 

DRAM, 

FLASH, 

Cache 

ROM 

● 10-100x higher data rates 

● Multimode operation 

Technologies 

Cost 

Configurable 

& 

programmable 

Modules and 

Logic 

● SoC - CMOS frequency ~ 500 MHz 

● DSP/µC, RISC + reconfigurable HW 

● at “GSM level” 

Time to market 

● 2 x faster than GSM 

mixed signal RF 

=> need for totally new design 

flows to support Wireless 

Design Platform concepts 

=> assisted generation of HW & SW 

from high level descriptions 

will be a key enabler for this 

capability


3G Baseband HW: software- 

definable radio 

Partitioning between processors, programmable (SW) 

and configurable hardware 

Performance vs. adaptability 

Accelerators and configurable HW in digital front end 

where processing speed requirements are high 

Processor cores (DSP / RISC/ CISC) support design 

reuse and risk mitigation 

Assisted generation of HW & SW from high level 

descriptions will be a key enabler for this capability


Composition & Interaction in 

MPEG-4


Computer 

MPEG-4 Industries 

! 

# 

$% 

"!!! 

Communication 

Entertainment


An Example of an MPEG-4 

Audiovisual Scene


Application Focus: 

Communications and Information 

Processing


System Level Design: Driving 

Complexity 

Forces 

What worked at 50K gates won’t 

work at 500K 

Integration 

HW & SW must be co-designed 

and co-verified 

The system is the chip...drives 

full-system simulation! 

Application knowledge is critical 

Quality Reliability, Risk 

Higher volumes, faster ramps & quality expectations mean 

higher risk 

Time to Market 

The right product in minimum time


Next generation tools 

3G/3C Design Challenges 

Tools 

Analog front end 

Application know-how 

Wireless 

Design 

Methodology 

nanometer design 

Multistandard design platform 

Reconfigurable HW 

DSP technology 

embedded hardware 

embedded software


Services to Enable Successful 

IP Block Design Flow 

System 

Synth 

Verify 

Test 

Layout 

Customized 

Flows 

IP & Libraries 

PLL 

RISC 

Core 

CACHE 

Third Party 

IP 

Security 

Encryption 

EEPROM 

RAM 

FLASH 


Core 

Glue 

Logic 

Digital 

Mod/De-mod 

ROM 


Blocks 

I/O 

Interfaces 

PIO 

RTC 

DMA 

USB 

1394 

PCI 

Protocol 

Decoder 

DRAM DAC 

A/D 

SoC Design 

SoC 

Design Reuse 

Methodology 

Design & Verification 

Assistance


Design Requests 

Solution 

High-Level Design 

● System Design 

● Synthesis 

● Reuse 

● Verification 

● Models & Libraries


Network 

building 

blocks 

HW 

Implementation 

HW 

Verification 

System-Level 

Design Entry 

RAM 

DSP core 

ROM 

Simulator 

Bus 

uP 

Digital Communication 

Model Library 

Network 

building 

blocks 

analog/ 

mixed 

signal 

I/O 

interface 

SW 

Implementation 

SW 

Verification 

DSP core 

SW 

uP 

SW


Methodology Roadmap Key 

!"# " 

Elements 

$ !"# % #& 

& & "


Libraries 

logic blocks 

From System-Level To 

Software and Silicon 

System-Level Design and Optimization 

Hardware/Software 

Partitioning 

How can you partition 

efficiently between 

HW/SW? 

cores 

Hardware Software 

' 

Do you wait for 

the HW to test the SW? 

Libraries 

Libraries


SOC Paradigm Shift 

Accelerates Design Process Through Design Re-Use 

Reduces Costs Through More Efficient/Higher ROI 

Silicon Manufacturing 

Expands Functional Capabilities Through Mix-and-Match 

Approach


An Evolution to Interface Based 

Verification 

# ( % ) 

* ( 

" + 

& , 

& - ( * 

# ( . 

& 

* ( 

+


Design, Verification, and 

Reuse Methods 

EACH Requires Expertise, Methods, 

Technology, & Previous Step


Design Challenges 

Interoperability and integration 

SOC designers can’t touch the glue logic like in board design 

virtual components may come from several forms 

System-level Integration 

various languages 

embedded processors 

develop the software for an as-yet-implemented hardware 

Block-to-block interface 

various on-chip buses 

EDA tool interoperability 

data format standards for complex design flow 

Testing an SOC 

it’s necessary to test each VC separately as well as the entire integrated chip. 

Bist, DFT, partial scan, full scan,… 

Process-level portability 

porting a hard VC from one implementation to another 

version control


Design Issues based on 

System-level 

Design Methodology 

Core-based Design 


Architectural Design 

Multi-disciplinary Design 

Productivity 

Orphans


Needs for Implementing 

Core Based 

Design Methodology 

Standard protocols and interfaces among 

blocks 

Challenge: create a minimal comprehensive set 

of protocols 

Inter-block communication protocol synthesis 

Reconfigurable interconnection 

Appropriate languages for SOC designs


Core-based Design 

Will have geographically-distributed design 

teams 

Cores will be used in unexpected ways: must 

have robust designs (e.g. TCP/IP) 

Stratification of designers 

Spend transistors to buy design ease 

Authors v.s. composers 

More importance on specification, 

characterization, standardization, process 

migration



Export (Core creation) 

implementation, tool support, documentation, test, 

customer support, etc. 

Import (Core selection) 

evaluation, qualification, compatibility, etc. 

IP Protection 

water mark, finger printing, encryption, etc. 

customer’s ease of use and verification 

Design reuse cost minimization 

Version control 

enhancements, process migration


Architectural Design 

Important Topics 

Architectural analysis and exploration 

Challenge: close the gap between system 

and RTL levels of design 

System-level partitioning and synthesis 

Design at higher levels of abstraction 

requires new views: core I/O, behavioral, 

software, cost, timing, power 

Power source control and management


Multi-disciplinary Design 

HW/SW design 

Co-specification, co-analysis, co-design and 

co-verification (co-x) 

HW/SW mapping and optimization 

Optimizing software for embedded applications 

Help software developer 

High-level power management and control 

Multi- disciplinary optimization including: 

packaging, mechanical, sensors, acoustical, 

optical, electrical, software


Productivity 

Move to higher levels of design 

abstraction 

Domain-specific design knowledge 

Design reuse 

Design time tradeoff 

Challenge: make design reuse easier as first 

use 

Must capitalize on disparate teams of 

designers from different geographic 

locations


Orphans 

System-in-package 

Error detection and recovery 

Fault diagnosis and repair 

Field test and diagnosis


Is there good solution for SOC? 

IP vendor? EDA? Foundry? Design 

House? ……...


What is System-on-a-Chip


Technology Improvement


/% #01 

!+2 

SOC Example 

& 

/1 

"/!


What did we do Yesterday? 

340"4 ( ( ( 

34 , 

% , 5 

1", ( 

# , prototype 

,




Reconfigurable Solution


Driving Associations 

Business and Legal 

Virtual Component Exchange (VCX) 

Fabless Semiconductor Association 

(FSA) 

Technology 

Virtual Socket Interface Alliance (VSIA) 

Reusable Application-Specific Intellectual 

Property Developers (RAPID) 

Silicon Integration Initiative (Si2)


Model of Complex IC Design Flow


VSIA Approaches 

-- Developing Working Groups 

Analog/Mixed-Signal 

Implementation/Verification 

System-level Design 

Manufacturing Test 

On-Chip Bus 

Virtual Component Transfer 

IP Protection



IP Models


System level Specifications 

Use to verify functionality of the VC in the chip or system context, 

verify the correctness of an RTL description in top-down design 

and to provide models for SW/HW co-verification. 

Executable Specification 

Guidelines: 

Verification Test Bench 

Behavioral Model 

Processor Model 

Instruction set Architecture 

Core size and performance estimator 

Software developing tools 

Run-time libraries 

Bus Functional Model 

Bonded out VC/Prototype


Chip-to-VC Hierarchical Integration 

Logical I/O Ports 

Re-entrant outputs should be avoided 

Through nets should be avoided


Chip-to-VC Hierarchical 

Integration(Cont.) 

When Tri-state capable output or bi-directional ports are used, 

tri-state enable/bi-directional control should be available at the 

VC boundary


Clocking Guidelines of Deliverable 

IPs --- recommended by VSIA 

Synchronous designs are preferred 

Single clock, single phase clock architecture are preferred. 

Clock port access should be properly identified by the VC 

provide. 

Clock characterization of the VC should be provided to the 

system chip designer, such as valid frequencies, skew 

requirements, duty cycle, and pulse width 

The VC designer should provide information on any special 

clocking requirements. 

When asynchronous signals are mixed with synchronous 

signals, the internal block design structure should be separate 

synchronous and asynchronous domains. The interface 

relationships between the blocks should be documented.


VLSI Tester Examples 

! " 

# $ % &' ( ) % 

*+ , ! , & , 

-+!. # - & ) & ) 

-+!. % 

-+!. +% /&/ /' /&/ /'


Test Tree


Test Tree (cont’)


Boundary scan Black Box VC 

External Scan 

Black Box VC 

Internal Scan 

Black Box VC 

* 

* 

* 

. 

$ 6 " 

$ 6 "


Boundary scan Black Box VC 

& # 

External Full 

Mux Interface 

& 1


 

! "#$% & 

' () * 

(+" 

,- . () 

,- . () 

/0 -% 

Case Case Case Design Design Design for for for 3G 3G 

3G 

Wireless Wireless Terminal Terminal 

Terminal 

⊗ 

µ 

 

µ


Layer Structure of MPEG2 

sequence 

layer 

GOP 

layer 

Bitstream 

header next layer 

picture 

layer 

slice 

layer 

Layer Function 

Video Sequence 

Group of Pictures 

Picture 

Slice 

Macroblock 

block 

macroblock 

layer 

Random Access Unit 

Random Access Unit 

Primary Coding Unit 

Resynchronization Unit 

Motion Compensation Unit 

DCT Unit 

block 

layer


Coded 

Data 

Basic MPEG-2 Decoding 

Variable 

Length 

Decoding 

Inverse 

Quantization 

Algorithm 

Inverse 

Scan 

Inverse 

DCT 

3 types of coded image frames: 

I Intra-coded frame 

P Predictive coded frame 

Framestore 

memory 

Motion 

Compensation 

B Bidirectionally predictive coded frame 

Decoded 

Pels


Proposed Architecture 

!


Profile Run Time


Low Power Design 

Consideration 

! 

" #$ 

% " &$'' 

!( '!( )* ) !& "$" 

!( '!( )* & + 

( , !& &


Co-Simulation 

" 

! 

# $


HW/SW Co-Verification 

Software Design Environment 

(C++ Language) 

Data Converter, Compare and Display 

Verilog or VHDL Hardware Simulator


HW/SW Co-Simulation


Simulation 

The reconstructed video frames of flow-garden 

sequence (352×240)


Simulation result 

The test sequence of small -size table tennis (128×128) 

The reconstruct video frame of MPEG2 sequence of 

cheer (704×480)


ROM 

RESET 

FPGA Board 

PCI 

EPF10K100ACR240-3 

240 pin 

ISA 

connector


MPEG-2 VIDEO version 1 

IDCT 

CONTROL 

VLD 

MC 

IQ 

IS 

Technology: 0.6 um cmos spdm 

Package : 256 CQFP 

Chip Size : 11.41 x 11.28mm2 Transistor count : 330191 

Power : 1.125 W 

Max Frequency : 28 MHz


MPEG-2 VIDEO version 2 

RAM 

IS 

RAM 

IQ 

VLD VG 

IDCT 

The MPEG2 video layout 

❐Technology: 0.6 um cmos sptm 

❐Package :130 pins 

❐Chip Size : 6.595 x 6.607mm2 

❐Transistor count : 228,772 

❐Max Frequency : 41.6 MHz


Conclusions 

Technology and Applications play key 

roles for System level design 

A lot of design challenges existed 

New design flow and methodology are 

necessary with global system design 

Multi-disciplinary design considerations


References 

A fast and low cost testing technique for core-based system-on-chip Ghosh, I.; Dey, S.; Jha, N.K. Design Automation 

Conference, 1998. Proceedings , 1998 , Page(s): 542 -547 

Applying hardware/software co-design to systems-on-a-chip Berger, A.S. Wescon/98 , 1998 , Page(s): 22 -28 

A rapid prototyping method for top-down design of system-on-chip devices using LPGAs Suzuki, F.; Koizumi, H.; Seo, K.; 

Yasuura, H.; Hiramine, M.; Okino, K.; Or-Bach, Z. Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 

Asia and South Pacific , 1997 , Page(s): 9 -18 

How VSIA answers the SOC dilemma Birnbaum, M.; Sachs, H. Computer Volume: 32 6 , June 1999 , Page(s): 42 -50 

Executing system on a chip: requirements for a successful SOC implementation Daeje Chin Electron Devices Meeting, 

1998. IEDM '98 Technical Digest., International , 1998 , Page(s): 3 -8 

RTL design source management for system-on-a-chip designs Blaner, B.; King, C.; Stabler, P.C. Wescon/98 , 1998 , 

Page(s): 147 -152 

Core design and system-on-a-chip integration Rincon, A.M.; Cherichetti, G.; Monzel, J.A.; Stauffer, D.R.; Trick, M.T. 

IEEE Design & Test of Computers Volume: 14 4 , Oct.-Dec. 997 , Page(s): 26-35 

A New Scalable Dsp Architecture for System on Chip (soc) Domains Weiss, M.H.; Engel, F.; Fettweis, G.P. Acoustics, 

Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on Volume: 4 , Page(s): 1945 - 

1948 

Hardware/software co-verification, an IP vendors viewpoint Hopes, T. Computer Design: VLSI in Computers and 

Processors, 1998. ICCD '98. Proceedings. International Conference on , 1998 , Page(s):242 -246 

Functionally integrated systems on a chip: technologies, architectures, CAD tools, and applications McShane, E.A.; Shenai, 

K. Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997 , 1998 , Page(s): 67 -75 

Future systems-on-a-chip: impact on engineering education De Man, H. VLSI '98. System Level Design. Proceedings. 

IEEE Computer Society Workshop on , 1998 , Page(s): 78 -83 

Web site of VSIA, VCX, Rapid, and IP design & reuse

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