The Esterel v5 21 System Manual - Courses

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8 CHAPTER 1. GETTING STARTED The advantages and drawbacks of automata are described in Section 2.3.3. As for sorted circuit code, a human-readable form of the automaton is printed in file foo.debug when typing the following command: esterel -Adebug foo.strl For more information about the emitted signals, type esterel -Adebug:"-emitted -names" foo.strl The ‘:’ symbol is used to pass a list of additional option to the final code generator. 1.3.4 Hardware Circuit Generation Pure Esterel programs are programs that only handle pure signals, i.e. that involve no types, constants, functions, procedures, tasks, valued signals, and variables. Only simple counters are allowed in Pure Esterel, as in “await 3 S” or “repeat 5 times” or “repeat N times” provided that N is an initialized integer constant. For Pure Esterel programs, one can also generate hardware circuit netlists. For example, to build a circuit from foo.strl, type esterel -Lblif foo.strl The -L option defines the target language, here the blif circuit description format (blif stands for Berkeley Logic Interchange Format). An actual circuit can be build from the foo.blif file by using logic optimizers and technology mappers not detailed here. Option -Ablif is also available to generate circuits based on explicit automata, although this is generally not a good idea. 1.4 The xesterel GUI If you prefer a graphical interface to a command line interface, use the xesterel GUI (Graphical User Interface). It can be used to generate and execute an esterel or xes command line, setting the various options by clicking on graphical objects. See the on-line documentation for more details. 1.5 Examples Chapter 7 contains basic examples. Their Esterel and C codes are in the documentation directory of the Esterel tar file together with this manual.
1.5. EXAMPLES 9 The distribution tar file also contains a non-trivial complete example: a wristwatch with timekeeper, stopwatch, and alarm. Go to the wristwatch directory, and read the README file. Print the file paper.ps that contains a description of the program (sorry, it is a rather old description, still valid however). Edit the Makefile appropriately, and try at least running the ww fullscreen simulation and the xww xes-based simulation. Click on whatever is red or blue in the source code windows and observe the result. Try different code generation options by changing the STRL FLAGS variable in the Makefile. Try in particular option -I for the fullscreen simulator xww that calls xes.
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Page 4 and 5: ii CONTENTS 2.5 Sanity Checks . . .
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Page 8 and 9: 2 PREFACE feedback. WARNING: Chapte
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100 CHAPTER 7. SIMULATION EXAMPLES
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112 CHAPTER 8. CONSTRUCTIVE CYCLIC
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Index !, see csimul ?, see csimul #
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124 INDEX ?, 85 combined signal, 88
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126 INDEX lc, 12, 13, 27 -lc, 15, 2
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128 INDEX scc, 13, 18 sccausal, 12,
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130 INDEX high/low inputs, 67, 72 i
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