Novel Power MOSFET Packaging Technology Doubles Power ...

3. Facilitate simplified board layout and
paralleling of devices.
4. Enable the use of existing surface mount
assembly lines and technology.
In order to achieve points 1 and 2 above, the
design of DirectFET technology has rationalised some
of the concepts and materials that are commonly used in
power packaging. This simplified approach is shown as a
cross section in Figure 2.0.
copper ‘drain’
clip
gate
connection
passivated die
copper track
on board
die attach
material
source
connection
FIGURE 2.0 – CROSS SECTION OF DIRECTFET TECHNOLOGY
The cross section in Figure 2.0 shows a
MOSFET die with the source face of the die soldered
directly to the printed circuit board. The drain connection
is then made from the back of the die to the board
through the use of a copper ‘can’ into which the die has
been bonded. The facilitator in this scheme is a new
proprietary passivation system developed by
International Rectifier. This passivation is applied to a
wafer that has a solderable top metal stack (rather than
an aluminium top metal commonly used for wirebonded
devices). It is then patterned to open out solderable areas
on the surface of the die for the source and the gate
connections. This allows the shape of the solder joints
between the silicon and the circuit board to be closely
controlled. The passivation has two very important roles
to play:
1. The passivation itself is unsolderable. This
means that whilst allowing close control of
the shape of the solder joints it also prohibits
solder shorting between the gate and source
contacts during the board mount process.
2. The passivation provides environmental
protection for the termination structure and
gate busses on the die. It is resistant to
moisture and ionic contamination that may be
found on the board or in the solder flux, etc.
With this passivation applied, the gate and source
connections can be made directly between the circuit
board and the die without any unnecessary leadframe or
wirebonds in series with the conduction path. Since the
construction of the MOSFET silicon used in DirectFET
devices is not that of a flipchip, i.e not all the
connections are on a single side of the die, the drain does
require a ‘leadframe connection’ to complete the
electrical circuit. The die is bonded into a copper clip or
‘can’ using a silver filled epoxy and the finished, fully
tested device can be board mounted in the same way as
any conventional surface mount component.
III. CONDUCTION PERFORMANCE
The rationalised approach taken with
DirectFET technology has greatly reduced the
conduction path through the package and removed the
high resistance elements. Figure 3.0 shows a comparison
of the conduction paths of this new technology versus
older SO -8 and newer Copperstrap SO-8 packages.
The comparison shows that DirectFET technology has
eliminated conduction paths and material interfaces
which all add resistance in series with the silicon die.
The effect is that the die free package resistance has been
reduced to less than 200μΩ, a reduction of 86% over the
SO-8 & approximately 74% over the Copperstrap SO-
8. This reduction in the series resistance means that in an
SO-8 outline typical R ds(on)values of 2mΩ are achievable.
FIGURE 3.0 CONDUCTION PATHS FOR SO-8 (TOP), COPPERSTRAP SO-
8 (MIDDLE) AND DIRECTFET TECHNOLOGY (BOTTOM)
IV. THERMAL PERFORMANCE
Whilst advances in conduction performance are
key to increasing the current density in power converters,
the issue of how to most effectively extract the heat from
these converters and thus increase power density still
applies. The direct nature of the coupling of the silicon to
the board means that DirectFET technology has reduced
the thermal resistance to the board. The thermal
resistance from junction to board of a standard SO-8
package is of the order of 20°C/W. However
DirectFET technology reduces this to 1°C/W as the
thermal resistance path runs through the top metal and