Intel at VLSI Fact Sheet.pdf

Fact Sheet
Intel Talks about Future Technologies for Processors,
Reveals New Details about 22nm 3-D Tri-Gate Transistors
New Innovations Presented at 2012 IEEE Symposia
on VLSI Technology and Circuits, June 12-15
June 12, 2012 – Intel Corporation is delivering myriad presentations, panel discussions and
demonstrations at this year’s VLSI Symposia. A highlight paper discloses new details about
Intel’s 22nm process – the industry’s first fully depleted 3-D tri-Gate technology with superior
low voltage and low power capabilities. Other Intel papers describe innovations in reducing
power consumption for graphics processing, advances in transistors made with compound
semiconductors, a viable option for future ultra-low power transistors, fundamental leaps in
energy-efficient computing and integrated digital radio and SoC technology.
Below are highlights covering Intel’s scheduled presence at the event.
Details on Intel’s 22nm Process with Tri-Gate Transistors
Chris Auth, 22nm front-end integration manager, describes Intel’s 22nm logic technology, the
first in the industry featuring fully depleted 3-D tri-gate transistors. This paper was selected by
the VLSI Symposia as a “highlight” paper. The fully depleted transistors provide significant
improvements in transistor switching characteristics, specifically record low sub-threshold slope
and DIBL. These transistors also incorporate a 3 rd generation high-k + metal gate technology and
a fifth generation of channel strain techniques, resulting in the highest drive currents yet reported
for NMOS and PMOS. The technology is optimized for high performance and low power,
offering triple threshold voltage transistors with different combinations of performance and
leakage. Self-aligned contacts are implemented to eliminate restrictive contact to gate
registration requirements, facilitating manufacturability. Interconnects feature nine metal layers
with ultra-low-k or low-k dielectrics throughout the interconnect stack. High-density MIM
(metal-insulator-metal) capacitors using a hafnium-based high-k dielectric are provided for
signal and decoupling applications. The technology is in high volume manufacturing in multiple
fabs.
Paper and contributors details:
15.2: A 22nm High Performance and Low-Power CMOS Technology Featuring Fully Depleted
Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitor, C. Auth, C. Allen,
A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T.
Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D.
Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyun, H. Liu, R.
McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S.
Ramey, T. Reynolds, J. Roester, J. Sanford, J. Seiple, P. Smith, C. Thomas, D. Towner, T.
Troeger, G. Weber, P. Yashar, K. Zawadzki, K. Mistry, Intel

Pushing Performance and Energy Efficiency Beyond the Traditional Limits
This research from Intel Labs, selected by the VLSI Symposia as a “highlight” paper,
demonstrates a test chip in 22nm tri-gate process that enables elimination of voltage droop
margins, safeguards that today protect against temporary voltage reductions that occur
occasionally during processor operation. Voltage droop margins leave performance and energyefficiency
on the table and removing them can significantly improve processor performance and
energy efficiency. This technique focuses on dynamically adapting the chip’s clocking to these
rare voltage reductions. While previous techniques have focused on detecting and correcting
occasional errors, this technique delays the occurrence of timing errors, automatically shuts
down clocking in the affected region before an error actually occurs, and then restarts when the
transient droop event goes away. Measurements demonstrate simultaneous throughput gains and
energy reductions ranging from 14 percent and 3 percent, respectively, at 1.0V to 31 percent and
15 percent at 0.6V for a 10 percent voltage droop.
12.1: A 22nm Dynamically Adaptive Clock Distribution for Voltage Droop Tolerance, K.
Bowman, C. Tokunaga, T. Karnik, V. De, J. Tschanz, Intel
Reducing Power for Processing Graphical Applications
This research test chip from Intel Labs is designed to make floating point calculations more
energy efficient, particularly for visual computations in future processor graphics engines.
Today, most graphical applications, such as games, use 32 bits of information to store and
calculate numbers when less would suffice. This test chip features a first-of-its-kind variableprecision
scheme that enables 24-, 12- and even 6-bit precisions, selecting the minimum
precision needed to optimize efficiency. This scheme has the potential to cut power in half for
some graphics applications. This research focuses on innovations in the register files used to
store the variable-precision numbers feeding the floating-point unit. The register file also utilizes
near threshold voltage (NTV) circuits to enable ultra-low power processing. Measurements
demonstrate read/write operations over a wide dynamic voltage range spanning 1.2V down to
350mV and a peak energy-efficiency of 751 billion operations per watt (at 400mV) for low-
precision calculations – an improvement of more than 20x over full-precision calculations at
nominal voltage. In addition, it enables 19 perecent area reduction for these register files,
enabling smaller and more cost-effective chips.
14.5: A 2.8GHz 128-entry x 152b 3-Read/2-Write Multi-Precision Floating-Point Register File
and Shuffler in 32nm CMOS, S. Hsu, A. Agarwal, M. Anders, H. Kaul, S. Mathew, F. Sheikh, R.
Krishnamurthy, S. Borkar, Intel
Intel’s Semiconductor Research Pipeline
Continued advances in electronics require not only better CMOS devices but improvements in
our ability to precisely fabricate novel materials and structures. This talk by Mike Mayberry,
Intel vice president and director of Intel’s Components Research, highlights some of the key
directions for the next few generations and then discusses opportunities for beyond CMOS
devices in the next decade.
1.1: Peering through the Technology Scaling Fog (Invited), M. Mayberry, director of
Components Research, Intel Corp.
Progress in Transistors Using Compound Semiconductors, for Ultra-Low Power Chips

Gilbert Dewey, senior device engineer, summarizes the performance of compound
semiconductor (III-V) field effect transistors (FETs) including thin body planar MOSFETs, 3-D
tri-gate MOSFETs, and Tunneling FETs (TFETs) for low-power applications. Due to inherently
higher carrier mobility, III-V MOSFETs are shown to have a significant low-power performance
advantage over state-of-the-art planar Strained Si MOSFETs. The sub-threshold slope (SS) and
DIBL in the III-V MOSFETs improve from thick body planar to thin body planar with further
improvement shown in 3-D tri-gate III-V MOSFETS. Beyond the MOSFET structures, subthreshold
slope steeper than the best possible MOSFET (

advanced circuit design technologies. Industry leadership results in SRAM performance, density,
and low-voltage operation will be presented.
10.1: SRAMs Design in Nano-Scale CMOS Technologies (Invited), K. Zhang, Intel
A Technology for Implementing Read-Only Memories in Intel’s 32nm Process
Anti-fuse technology for implementing on-chip one-time-programmable read-only memory
(OTP-ROM) holds the promise of achieving high-density ROM arrays with large-scale parallel
write ability. Example applications include on-chip encryption keys, microcode storage and dielevel
post-Si tuning. While earlier work has focused on earlier polysilicon-gate SiO2/SiONbased
technology generations, in this paper, Sarvesh Kulkarni, senior design engineer, Intel
presents the first demonstration of anti-fuse memory in high-k + metal gate CMOS. The paper
presents a 1.01µm2 one-transistor one-capacitor (1T1C) bit cell that is the smallest in literature.
The technology incurs zero cost overheads over the underlying SoC process and demonstrates a
high-density array architecture that meets reliability requirements and is programmable at 4.5V.
9.2: A 32nm High-K and Metal-Gate Anti-Fuse Array Featuring a 1.01μm2 1T1C Bit Cell, S.
Kulkarni, S. Pae, Z. Chen, W. Hafez, B. Pedersen, A. Rahman, T. Tong, U. Bhattacharya, C.-H.
Jan, K. Zhang, Intel
Fine-Grained Power Management for Processors and SOCs
In chips today, different regions of a chip often share a common voltage source, which may not
be the most efficient choice in terms of performance and power consumption for different
circuits. Energy efficiency can be improved by enabling multiple independent voltage domains
and fine-grain power management, so that each region on a processor or SOC can run at an
optimum voltage. This research from Intel Labs describes a technique to efficiently generate
many different voltages on the chip from a single voltage source coming into the chip from a
platform voltage regulator on the board. This fully digital linear voltage regulator can be
sprinkled across the chip to allow fine-tuning and control of voltage levels independently per
region. It is capable of operating across a wide range of input voltages and currents, and provides
a conversion power efficiency that is as high as 97 percent of the ideal efficiency limit. Being
fully digital, the regulator design can be migrated efficiently across process technology nodes,
and is flexible as well as area-efficient. This technique will allow fine-tuning of a wide variety of
circuits in future processors and SoC’s to provide tolerance of process and environmental
variations, and achieve better performance and energy efficiency.
17.5: Fully-Digital Phase-Locked Low Dropout Regulator in 32nm CMOS, A. Raychowdhury, D.
Somasekhar, J. Tschanz, V. De, Intel
Helping Chips Optimize their Data I/O Links
Timing accuracy of clocking circuits is critical to achieve performance targets of high-speed I/O
links. The calibration and correction of clocking and timing issues caused by process, voltage
and temperature variations in I/O links of chips in high-volume manufacturing pose major
challenges for external testing equipment and test time. This research from Intel Labs adds a key
capability to help chips optimize their own I/O links for maximum data rate and energy
efficiency by monitoring test-time or run-time timing variations with a high degree of accuracy.
This capability is enabled by an on-die, all-digital delay measurement circuit that precisely
characterizes timing with an accuracy of 250fs (250 quadrillionths of a second). The all-digital

approach promises easier migration, better area efficiency and better scalability across future
process technology nodes.
12.3: An On-Die All-Digital Delay Measurement Circuit with 250fs Accuracy, M. Mansuri, B.
Casper, F. O'Mahony, Intel
Scaling Digital Radio
Process constraints are unfriendly to radio frequency performance, and make it a challenge to
integrate RF into advanced digital CMOS manufacturing processes. This paper presents a WiFi
transceiver in 32nm CMOS process that could potentially scale down in size and power
consumption as it would transition to more advanced manufacturing process technologies in the
future.
10.2: A 2.4GHz WLAN Transceiver with Fully-integrated Highly-linear 1.8V 28.4dBm PA,
34dBm T/R Switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS, Y. Tan, J.
Duster, C.-t. Fu, E. Alpman, A. Balankutty, C.C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar,
H. S. Kim, B. Carlton, S. Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala, Intel Corporation
-- 30 --
Intel, the Intel logo and Atom are trademarks of Intel Corporation in the United States and other countries.
* Other names and brands may be claimed as the property of others.
CONTACTS: Connie Brown Radoslaw Walczyk
503-791-2367 408-765-0012
connie.m.brown@intel.com radoslaw.walczyk@intel.com