LP DK 790FX BIOS Setting Guideline - Dfi

2T mode: Command rate mode 1T and 2T, Enable for 2T
CAS latency Time (Tcl): 3~6 clocks; CAS (Column signal) latency time
Precharge Delay (Tras): 5~18 Minimum timing of a command working cycle. (TRCD+CL+ 2 clock)
DRAM RAS# Precharge (Trp) : 3~6 clock; Precharge timing for memory data by each command
cycle
DRAM RAS# To CAS# Delay (Trcd): 3~6 clock; RAS (Row signal) to CAS (Column signal) delay for
read/write command
Bank to Bank Delay (Trrd): 2~5 clocks; Command rate of memory's banks
(Trc): 11~26 clocks; Minimum timing of a command to next command. (tRC) = (tRAS)+ (tRP)
(Trtp): 2~5 clocks; Precharge period for read action
(Twr): 3~6 clocks; Write recovery timing
(Twtr): 1~3 clocks; delay write to read command for memory chips
(Trfc0): 75~327ns; Minimum timing to reflash a ROW at same storage block(tRFC > tRC)-DIMM1 slot
(Trfc1): DIMM 2 slot
(Trfc2): DIMM 3 slot
(Trfc3): DIMM 4 slot
(Trdrd): 2~5 clocks
(Trwrd): 3~9 clocks
(Twrrd): 0~3 clocks
(Twrwr):1~3 clocks
CS/ODT Pin fine Delay: Enable /Disable DRAM terminal impedance/voltage optimized
*TBL Cache mode: Enable /Disable TBL cache for Phenom DRAM controller
Bank Swizzle Mode: Enable /Disable DRAM device Bank address bit remapping function
AUTO Tweak Performance: Enable/Disable MCT optimized parameters
Optimized performance mode: Enable/Disable
Enable performance mode for DIMMS with peformance SPD. This provides an opportunity to
adjust/scale or manually enter (from setup engine for example) controller; cycle times
(CL,Trcd,Trp,Trtp,Tras.Trc,Twr.Trrd,Twtr,Tfrc(x))
* item is for AMD Phenom CPU only