LP DK 790FX BIOS Setting Guideline - Dfi

P-states called P-states 0 through 4 or P0 though P4. P0 is the highest power, highest
performance P-state; each ascending P-state number represents a lower-power, lower
performance P-state than the prior P-state number. At least one enabled P-state (P0) is
specified for all processors.
HT Link Control :
HT Link Width: 16bit/8bit mode, CPU to NB bus hyper transfer bandwidth
HT Link Frequency: 200~2600MHz (2.6GHz), CPU to NB bus hyper transfer speed
IH Flow-Control Mode: Enable to support the use of the Isochronous Flow-Control Mode function to
provide reduced latency for certain classes of southbridge traffic
HT Link Tristate: Enable to tristate parts of the link in order to reduce power consumption. By default,
no lanes are tristated. The CAD and CTL lanes may be tristated together or CAD, CTL, and CLK may
be tristated.
2X LCLK Mode: nil (will be removed by next version)
UnitID Clumping: Enable to support UnitID clumping to increase the number of outstanding requests
supported by a single device. It maybe enabled for PCI-Express GFX links in certain configurations.
Clumping may be enabled when using only the lower number bridge within each PCI-Express GFX
core
PWM Setting :
PWM Control: Enable/Disable to open Voltage control function
CPU VID Special Add: plus on CPU voltage.