LP DK 790FX BIOS Setting Guideline - Dfi

LP DK 790FX BIOS Setting Guideline
(BIOS version: 01/22/2008) V001
Pressing DEL at DFI DK 790FX LOG screen to login BIOS setup screen
BIOS setup screen
L

Genie BIOS settings: This setup thread is combined all needed settings for over clocking
(CPU speed setting, CPU features, DRAM timings, Voltage settings and PCI speed etc.)
Genie BIOS : Main setup screen
Timing Mode: Manual to control Memory Clock Value/Limit or AUTO by SPD detecting
Memory Clock Value or Limit: 400~1066MHz; DRAM working ratio
CPU Clock Ratio: 4/4.5~ 24.5x; CPU multiplier definition , by CPU type up to 24.5
AMD K8 Cool&Quiet control: Enable/Disable AMD CPU advance power control function
Spread Spectrum: Disable/Enable for reducing clock consumption
CPU Host/HTT Cloock: 200~700MHz, CPU to NB bus working FSB
CPU Host/HTT Boot Up Clock: 200~700MHz; First stage OC speed
CPU Host/HTT Adjust Gap: 1~255 MHz; Frequency translating gap
PCIE Clock: 100~250MHz; PCIE slot working frequency
*CPU TLB Cache Fix: Enable /Disable TBL closed patch for Phenom DRAM controller
*(Press F8 to boot for showing this item, Phenom CPU only)
Onboard Devices :
Onboard LAN1: Rear LAN1port controller, default AUTO (enabled)

DRAM Configuration :
*DCTs Mode: DRAM controller definition; Ganged (dual controller) / Unganged (single controller)
*item is for AMD Phenom CPU only
MCT Memory Timing :
This page is defining the DRAM signal strength for each Clock and Data bus, in order to work on higher
working speed for tight DRAM timing.
MCT Memory Timing: Auto by detecting SPD and Manual to adjust
Maximum Latency: 1~15ns
The maximum asynchronous latency is the maximum round-trip latency in the system from
theprocessor to the DRAM devices and back. MaxAsyncLat is the sum of two components:
1. The worst case delay setting for DqsRcvEnDelay
2. A constant of 2ns associated with the delay internal to the processor

2T mode: Command rate mode 1T and 2T, Enable for 2T
CAS latency Time (Tcl): 3~6 clocks; CAS (Column signal) latency time
Precharge Delay (Tras): 5~18 Minimum timing of a command working cycle. (TRCD+CL+ 2 clock)
DRAM RAS# Precharge (Trp) : 3~6 clock; Precharge timing for memory data by each command
cycle
DRAM RAS# To CAS# Delay (Trcd): 3~6 clock; RAS (Row signal) to CAS (Column signal) delay for
read/write command
Bank to Bank Delay (Trrd): 2~5 clocks; Command rate of memory's banks
(Trc): 11~26 clocks; Minimum timing of a command to next command. (tRC) = (tRAS)+ (tRP)
(Trtp): 2~5 clocks; Precharge period for read action
(Twr): 3~6 clocks; Write recovery timing
(Twtr): 1~3 clocks; delay write to read command for memory chips
(Trfc0): 75~327ns; Minimum timing to reflash a ROW at same storage block(tRFC > tRC)-DIMM1 slot
(Trfc1): DIMM 2 slot
(Trfc2): DIMM 3 slot
(Trfc3): DIMM 4 slot
(Trdrd): 2~5 clocks
(Trwrd): 3~9 clocks
(Twrrd): 0~3 clocks
(Twrwr):1~3 clocks
CS/ODT Pin fine Delay: Enable /Disable DRAM terminal impedance/voltage optimized
*TBL Cache mode: Enable /Disable TBL cache for Phenom DRAM controller
Bank Swizzle Mode: Enable /Disable DRAM device Bank address bit remapping function
AUTO Tweak Performance: Enable/Disable MCT optimized parameters
Optimized performance mode: Enable/Disable
Enable performance mode for DIMMS with peformance SPD. This provides an opportunity to
adjust/scale or manually enter (from setup engine for example) controller; cycle times
(CL,Trcd,Trp,Trtp,Tras.Trc,Twr.Trrd,Twtr,Tfrc(x))
* item is for AMD Phenom CPU only

ODC control mode :
DRAM Drive Weak/Normal mode: Weak/Normal; Memories data bus drive mode.
Output Driver Comp: AUTO or Manual to adjust channel A/B drive strength abilities
CPU On-Die Termination: 300/75/50 ohm OTD terminator resister definition
DQS Drive Strength: 0.75 ~1.50x ; Memory data ready signal strength
Data Drive Strength: 0.75 ~1.50x ; Memory data bus signal strength
MEMCLK Drive Strength: 0.75 ~1.50x ; DRAM working clock signal strength
Addr/Com Drive Strength: 1.0 ~2.0x ; DRAM address signal strength
CS/ODT Drive Strength: 1.0 ~2.0x ; Memory modules BANK selection signals strength
CKE Drive Strength: 1.0 ~2.0x ; Clock available signal strength
CPU Feature: (Showing for Phenom CPU only )
*CPU DID: 1~16;
*CPU FID: 0000~003F; CPU COF = 100 MHz * (CpuFID + 10h) / CpuDID
Ex: FID=0Ah, CPU DID=2
CPU Speed= 100MHz *( 2Ch+10h)/2 ; 100MHz * (44+16)/2=100MHz * 30=3000MHz
*CPU-NB DID: 1~2;
*CPU-NB FID: 0000~001B NB COF = 200 MHz * ([NbFID + 4h / NbDID.
*AMD CPU Stepping: P-states are operational performance states (states in which the processor is executing
instructions, running software) characterized by a unique frequency and voltage. The processor supports up to 5

P-states called P-states 0 through 4 or P0 though P4. P0 is the highest power, highest
performance P-state; each ascending P-state number represents a lower-power, lower
performance P-state than the prior P-state number. At least one enabled P-state (P0) is
specified for all processors.
HT Link Control :
HT Link Width: 16bit/8bit mode, CPU to NB bus hyper transfer bandwidth
HT Link Frequency: 200~2600MHz (2.6GHz), CPU to NB bus hyper transfer speed
IH Flow-Control Mode: Enable to support the use of the Isochronous Flow-Control Mode function to
provide reduced latency for certain classes of southbridge traffic
HT Link Tristate: Enable to tristate parts of the link in order to reduce power consumption. By default,
no lanes are tristated. The CAD and CTL lanes may be tristated together or CAD, CTL, and CLK may
be tristated.
2X LCLK Mode: nil (will be removed by next version)
UnitID Clumping: Enable to support UnitID clumping to increase the number of outstanding requests
supported by a single device. It maybe enabled for PCI-Express GFX links in certain configurations.
Clumping may be enabled when using only the lower number bridge within each PCI-Express GFX
core
PWM Setting :
PWM Control: Enable/Disable to open Voltage control function
CPU VID Special Add: plus on CPU voltage.

SB PLL 1.2V Voltage range: 1.20V~1.50V, South bridge working voltage.
DRAM Voltage range: 1.8V~3.375V
NB Core Voltage: 1.12V~1.50V, CPU to NB bus voltage
NB PCIE Voltage: 1.12V~1.50V, CPU to NB bus voltage
NB HT Voltage: 1.04V~1.50V, CPU to NB bus voltage
PCIE Configuration: (Advance chipset feature)
GPP Power Limit: 0~255W
PCIE Slot1: First PCIE 16X slot configuration setting
PCIE Slot2: Second PCIE 16X slot configuration setting
PCIE Slot3: 3 rd PCIE 4X slot configuration setting
NB-SB Port Feature: HT link configuration setting
Gen2 High Speed Mode: Disable/software/Autonomous for PCI E Gen2 function
Link ASPM: Disable/L0s/L1/L0s&L1;
Link Width: 1~16X
Slot Power Limit, W: 0~255W

BIOS Reloaded function: DFI Lan Party series are providing 1last fine status + 4 user’s profile
space for doing BIOS setting saving and recovery.
Auto Save bootable setting: Enable / Disable
For saving last fine/ bootable parameters by BIOS itself every time
Load last bootable:
For loading last BIOS parameters.
Save setting to bank with: Current settings or last saved CMOS settings.
To define the resource of parameters for bank saving.
User define setting bank #1 ~ #4:
1. Bank Description: There are 4 rows for writing a short description. Double click on row when this
row is empty, it will erase pervious data.
2. Save to this bank: Press “Y” to save data to this bank
3. Load from this bank: Press “Y” to load data of this bank to be current BIOS setup settings.
4. Hotkey =>: define the “hotkey” for a quick change BIOS settings to boot. Please press Hotkey after
power on system immediately.
EZ Clear CMOS methods:
a. EZ Clear Jumper

. To hold Home key to power on system, BIOS will recover FSB to default, remains setting will be
keeping the last time fine status.
c. To hold Insert key to power on system, BIOS will load all setting back to default as like doing a
CCMOS by manually.
End