CAD DFM Guidelines.cdr

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Trace Width and Spacing Trace Trace Trace Trace Parameter Standard Advanced TO Trace Width (Outer Layer) 0.005 0.002 (*) STO Space Between Traces 0.005 0.002 (*) SPO Space Between Trace and Pad 0.005 0.003 (*) TI Trace Width (Inner Layer) 0.004 0.002 (*) STO Space Between Traces 0.004 0.002 (*) SPO Space Between Trace and Pad 0.004 0.003 (*) (*) Dynamic Details, Inc. TO STO SPO TI STI SPI Trace to Board Edge Parameter Standard Advanced SE Trace to Edge Spacing 0.010 0.006 (**) (**) Velie Circuits Trace SE NOTE: If the PCB edge is to be de-tabbed or V-Scored, traces should be a minimum of 0.050" away from the edge. This is an assembly issue, not a PCB manufacturing issue. Pad Pad 2
Plated Through Holes Parameter Standard Advanced T Board Thickness (max.) 0.093 0.300 (*) D Min. Drill Hole Diameter 0.012 0.006 (**) F Min. Finish Hole Diameter 0.008 0.004 (**) AO Min. Outer Layer Annular Ring 0.006 0.005 (*) AI Min. Inner Layer Annular Ring 0.005 0.004 (***) C 1 Clearance, Drill to Plane 0.015 0.011 (**) T/D Max. Aspect Ratio 10:1 12:1 2 Diameter Tolerance +/- 0.003 +/- 0.002 (***) Location Tolerance +/- 0.005 +/- 0.003 (**) (1) Plane clearance is normally specified as (pad diameter + XX mils; XX = 0.018" to 0.016") or (Drill diameter + YY mils; YY = 0.010"). The Clearance number was arrived at by adding 3 mil finish tolerance (can vary between 0.004 to 0.006) to the Inner Layer Annular Ring dimension and 5 mil (min) clearance between pad and plane. (2) Diameter Tolerance is normally +/- 3 mils for 12 mil diameter holes or larger; +0/-10 mils for smaller holes. Solder Mask W T F D AO C AI VP VN Parameter Standard Advanced T Registration Tolerance 0.003 0.002 (***) W Minimum Webbing 0.004 0.003 (***) VP Via Clearance (PTH) 0.003 0.002 (***) VN Hole Clearance (Non-PTH) 0.005 0.004 (***) (*) Dynamic Details, Inc. (**) Velie Circuits (***) Multek T 3
Page 1 and 2: Spirent Communications Performance
Page 3 and 4: 1) Companies used to create these g
Page 5: Non-Plated Holes Parameter Standard
Page 9 and 10: Anti-Pad/Plane Relief Parameter Sta
Page 11 and 12: Laser Drilled Micro-Vias Advanced O
Page 13 and 14: Fiducial Requirements 1. Local fidu
Page 15 and 16: For 0.062" think (max.) Printed Cir
Page 17 and 18: Test Points Preferred: ICT testing
Page 19 and 20: SMT Component-to-Component Spacing
Page 21 and 22: Additional Secondary Side Restricti
Page 23 and 24: 2. If BGA's are on both sides of th
Page 25: Required Files for PCB Assembly Req

CAD DFM Guidelines.cdr

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