Post Synthesis Simulation Using NCLaunch(NC ... - DAIICT Intranet

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Now we need to set the work directory and create a work library (to contain your circuits) so go to File -> Set Design Directory from the File menu of the Menu Bar. First set the design directory to the netlist_simulate directory that you just created (this should be automatic if you started NCLaunch from the tutorial directory as described here): then click on Create cds.lib File and click Save (you should only need to do this once when you run the tool for the first time). and finally click OK to Include default libraries. Finally, making sure that worklib has appeared for Work Library click OK on the Set Design Directory pop-up window. Please notice that the Library Browser window (right side) of NCLaunch has become populated now.
There are 3 steps that we need to perform now (remember we chose multistep): Compile (ncvlog) Elaborate (ncelab) Simulate (ncsim) 1. In order to compile you first need to select the various files in the File Browser (left side) by clicking on the mouse left button (simultaneously press on shift for multiple selections), then click on the corresponding buttons in the Menu Bar (in this case the ncvlog button) or explicitly go to Tools -> Verilog Compiler. You can edit the verilog files from File -> Edit. 2. In order to elaborate first click on the + in front of the worklib on the Library Browser window in order to see its contents:
Page 1: Work station access through NFS : O
Page 5 and 6: 3. To simulate click on the + sign

Post Synthesis Simulation Using NCLaunch(NC ... - DAIICT Intranet

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