Laboratory 4 A MIDI Interface - Department of Electronics at Carleton ...

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Carleton University Description of the Blocks Description of the Blocks The STRT_STP Block Refer to the timing diagram Fig. 4.9. Note particularly: Region B is shaded . Region C is shaded . Note the values of SI, DATAVALID and ACTIVE in the regions A, B, and C. Region C is when SI is not active, that is idle. See Fig. 4.4. When Region A is where ACTIVE starts up, but before DATAVALID goes false (low). Design the circuit to generate the ACTIVE signal from SI and DATAVALID. FIGURE 4.9 Timing used to generate the circuit for STRT_STP SI DATAVALID 0 1 0 ACTIVE B C A Complete truth table, Karnaugh map and schematic for STRT_STP. With proper use of don’t cares, you will need only one 2-input gate. Don’t cares come from impossible inputs; why cannot DATAVALID stay 0 in region C? DIVBY8 This circuit basically divides the clock by 8 to get a 32.0µs time base, which is used to generate a single 4µs pulse every 32.0µs.. ACTIVE CE CLK RST Q0 Q1 Q2 to where? CLR = ASYNCHRONOUS RESET CE = CHIP INPUT ENABLE CARRY OUT “TC” ON 7 COUNT Care must be taken to only sample the SI signal when it is stable. One way is to read SI in the middle of each bit. Since CLK is 8 times the bit rate of SI, this can be done sampling the first bit after 4 CLK pulses and MIDI-6 SWITCHING CIRCUITS © J.Knight, March 1, ’06 D C CE D C CE D C CE Q CLR Q CLR Q CLR TC Q0 Q1 Q2 stop bit Q0 + = ( Q0 )·CE + Q0·CE On the flip-flops CE = Clock Enable (Chip Enable) The Q output will not change unless CE is high. 1 1 FIGURE 4.10 A 3-bit binary counter you will need to modify Q1 + =( Q0⊕Q1)·CE + Q1·CE fdce in the Xilinx libraries Use fdc if CE is not needed. Q2 + = (Q2⊕(Q1·Q0)·CE + Q2·CE Where should ACTIVE be placed in these equations?
then every 8 pulses thereafter. A counter which counts up to 8, can do the proper frequency division. The most significant bit Q2 will change at 1/8 of the clock frequency. A typical binary counters is shown in Fig. 4.10. This counter has an output called TC (terminal count). It gives a pulse, one clock cycle wide, every 8 clock cycles (every count of 7). TC was designed to trigger another counter to allow the two counters to count to 64. If you are counting every clock cycle you do not need CE. The circuit shown can be modified to give an output after 4 clock cycles (a count of 3) and every 8 cycles thereafter. It should also be modified so the count goes to zero when ACTIVE goes low. This should be done synchronously, on a clock edge, by feeding zeros to the D inputs. Don’t even think about using the asynchronous CLR for this. This counter is a starting point for DIVBY8, but some of the names and circuitry are different. For example TC and GoToZero will need to be changed. It may help to look at the state graph on p.10. The CONTROL Block This circuit counts the SAMPLE pulses and generates two signals from the count: 1) The QUIT signal tells the serial-to-parallel shift-register that all the data-bits are read, and it should stop shifting. Note there is a difference between all the data-bits, and all the data-bits plus the stop bit. 2) The DATAVALID signal turns off ACTIVE. DATAVALID must be 1 at the very start of the START-BIT in SI to initiate raising the ACTIVE signal. This circuit needs to count 10 sample pulses, start, 8 data bits and stop. This is a decimal counter. Such a counter has Q0, Q1 and Q2 exactly like the previous binary counter. However Q3 must be added. Note the state after nine is not ten, but zero. If you have designed the previous counter to synchronously go to zero on a count of three, then you know how to make this counter go to zero synchronously after a count of nine. Note the counter chip enable (CE) holds the counter at its old count until enabled by SAMPLE. Hence use flip-flops with chip-enable (Xilinx cell fdce) in this design. Alternate CONTROL Block One does not need to design a separate counter. The shift register described in the SER2PAR block can keep track of the number of bits coming in. Use an extra D flip-flop and a gate to clear or set every flip-flop on the 11th SAMPLE pulse.You must be able to tell when the input SI has finished, no matter what the data is. RST CLK SI DATAVALID STRT_STP FIGURE 4.11 The SER2PAR Block You need to design an 8-bit serial-in/parallel-out shift register in which you can serially shift in the data bit values as they are read. Run the flip-flops from the 4ms clock, but use the CE (chip enable) inputs so they are effectively DIVBY8 ACTIVE SAMPLE RST DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 © J.Knight,March 1, ’06 SWITCHING CIRCUITS MIDI-7 SI DATAVALID SER2PAR2 DATA0 should be the 1st bit after START RST D C CLR Q=data4 D C CLR Q=Data3 D C CLR Q-Data2 D C CLR DATAVALID Q=Data1 D C CLR Q=Data0
Page 1 and 2: CARLETON UNIVERSITY Deparment of El
Page 3 and 4: low for ~14µs so that its high par
Page 5: SI Serial In RST CLK The flip-flops
Page 9 and 10: SI CLK In the simulation the incomi

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