CARLETON UNIVERSITY Laboratory 2.0 - Department of ...

CARLETON UNIVERSITY
Department of Electronics
97.267 Switching Circuits January 23, 2002
Overview
Laboratory 2.0
A 3-Bit Binary Adder/Subtracter
“If the facts don’t conform to theory, they must be disposed of.” From Fiedler’s Forecasting Rules
A binary adder finds the sum of two binary numbers say X = x2x1x0 and Y.= y2y1y0 The adder, you will build, will find the sum or difference of two 3-bit two’s-complement binary numbers,
and show the result on three output lines.
It will also detect overflow when the sum of two numbers is too large or small to be correctly represented.
FIGURE 1 A block diagram of the circuit and some examples. The examples are explained later.
Two’s Complement Numbers
3-bit numbers
+3 011
+2 010
+1 001
0 000
-1 111
-2 110
-3 101
-4 100
4-bit numbers
+7 0111
+6 0110
+5 0101
+4 0100
+3 0011
+2 0010
+1 0001
0 0 0 0 0
-1 1111
-2 1110
-3 1101
-4 1100
-5 1011
-6 1010
-7 1001
-8 1000
3 DATA BITS x2 x1 x0 LEAST
SIGNIFC
y
BITS
3 DATA BITS
2
y1 y0 SUBT/ ADD
SWITCH
3-BIT, TWO’S COMPLEMENT
ADDER/SUBTRACTOR
© J.Knight, January 23, ’02 SWITCHING CIRCUITS Lab2-1
OVF
s 2
s 1
Examples
Y X S
y 2 y 1 y 0 x 2 x 1 x 0 s 2 s 1 s 0 OVF
(+1) + (-1) 0 0 1 + 1 1 1 0 0 0 0
(+2) + (+2) 0 1 0 + 0 1 0 1 0 0 1
(+3) + (-4) 0 1 1 + 1 0 0 1 1 1 0
(-1) + (-4) 1 1 1 + 1 0 0 0 1 1 1
(+3) + (+3) 0 1 1 + 0 1 1 1 1 0 1
(-3) + (-2) 1 0 1 + 1 1 0 0 1 1 1
(-1) - (-4) 1 1 1 - 1 0 0 0 1 1 0
( 0)- (-4) 0 0 0 - 1 0 0 1 0 0 1
( 0)- ( 0) 0 0 0 - 0 0 0 0 0 0 0
s 0

Carleton University
Background
Two’s Complement Numbers
3-bit
two’s complement
numbers
These are a method of representing negative numbers.
+3 011
It is used because both positive and negative numbers can be added on the same
hardware, and because a few gates will convert an adder into a subtractor.
+2
+1
0
010
001
000
Negative numbers all start with “1”. The most significant bit is “1”.).
-1
-2
111
110
There is one more negative number than positive number.
Two’s complement numbers look just like positive binary integers, and one
-3
-4
101
100
adds them the same way. They are two’s compliment only in the way you interpret them.
Addition Of Binary Numbers, Including Two’s Complement Numbers
FIGURE 2 Two’s complement binary addition example
+
(+3) 0 1 1
1 1 0 Carry
(- 2) 1 1 0
0 1 1 + 1 1 0
Normal binary adds use the off-end carry.
With 2’s complement numbers, ignore it
(+1)
To add two two’s complement numbers, add them bit-by-bit being sure to transfer the carries
over to the next column. In normal binary adds, the off-end carry is part of the number. Thus if two
three-bit numbers are added, the result may be a four-bit number. This is shown in the little box on
the right of Fig. 2 (p. 2).
With two’s complement numbers the final off-end carry is ignored so the result of adding two
3-bit numbers is always a 3-bit number. All the adds in this lab will be two’s complement adds.
Notice the adder gives the same result in both cases. If we say it is a two’s complement addition
we ignore the off-end carry. If the rest of the number starts with a “0” we read it like any positive
binary number. If leading bit of the rest of the number is “0”, look it up in the tanle, or read the
next section.
If one does the same addition on the same hardware, but says that the bits represent positive integers,
one gets the result shown in the box in Fig. 2 (p. 2). One looks at the off-end carry and one
reads the answer as a positive number. We will not use this type of addition in this lab.
To Take The Two’s Complement Of A Binary Number
1. Invert each bit.
2. add 1
3. ignore any carry.
Example: Take the 2’s complement of +1 (001 in binary).
Take 001, invert bits110
add one 1
111 (111 is ‘-1’ in 2’s complement)
Find the 3-bit two’s complement of +3, -2, -1, -4. using the method above. (You will be asked to do
this in the prelab.)
Lab2-2 SWITCHING CIRCUITS © J.Knight, January 23, 2002
1
0
0
1
+ (+3)
(+6)
1
0 1 1
1 1 0
(+9) 1 0 0 1
Regular binary addition
Not 2’s complement
1
0

What is special about the 3-bit two’s complement of -4?
The Half Adder, an Adder for Two Single-Bit Numbers
This circuit can add 0+0, 0+1, 1+0, and 1+1. It gives a single-bit sum
output s i and a single-bit carry output c i+1
The Full-Adder, an Adder for Three Single-Bit Numbers
The half-adder is not enough for adding binary numbers. One must be able
to add three input bits. The third bit, “c i” will turn out to be a carry input.
An Iterative Adder Circuit for Multibit Numbers
One can make a multibit adder by combining full adders in an iterative circuit.
Iterative circuits are also called bit-sliced circuits
FIGURE 3 A 3-bit adder made from three full adders..
Not part of sum with 2’s
complement numbers
The carry output of one full-adder is sent to the next full-adder. In the above picture, “c 3 ” is ignored
in two’s complement addition. “c 0 ” is always zero since their is no carry input
Adding Multibit Two’s Complement Numbers
The advantage of two’s complement numbers is that negative numbers, are added exactly the same
way positive numbers. Thus the positive integer adder circuit in Fig. 3 (p. 3) could be used for adding
two’s complement integers.
However, unlike 3-bit positive integers, you cannot add 3-bit two’s complement integers to get a 4bit
number. The carry out c3, is never part of the sum.
A Two’s Complement Subtractor
To calculate Y-X, one adds Y to the 2’s complement of X.
~
To get the 2’s compliment, inverts the bits of X, to get say X and adds “1”. In summary,
Y - X = Y +
~
X + 1
A convenient way to add the “1”, is to use “c 0”.
A 2’s complement subtracter.
A Combination Adder-Subtractor
One can make a circuit that both adds and subtracts by:
(1) Having the inverters swithe in and out of the circuit by external control.
(2) Making the initial carry in, c 0 = 0 for addition and c 0 = 1 for subtraction.
c 3
This carry out will be used
to help detect overflow
y2 x2 FULL
ADDER
c2 © J.Knight,January 23, ’02 SWITCHING CIRCUITS Lab2-3
c 3
s 2
y 2
y1 x1 FULL
ADDER
c1 x 2
FULL
ADDER
s 2
z 2= ~ x 2
c 2
s 1
y 1
s 1
x 1
FULL
ADDER
y 0
c i+1
FULL
ADDER
c 1
s 0
y i
HALF
ADDER
c i+1
y i
s i
FULL
ADDER
x 0
s i
c 0
x i
x i
c i
~ ~ 1
z1= x1 y0 z0= x0 c0 FULL
ADDER
s 0
x 0

Carleton University
FIGURE 4 Making an adder into a combination add-subtract unit.t
The gate in the box, inverts “x i” when the control signal Sub(H)/Add(L) is High (1),
and passes “x i” with no change when Sub(H)/Add(L) is Low (0).
This is a fairly common logic gate. Can you give this gate’s name?
Detecting Overflow
SUB(H)/ADD(L)
SWITCH
The switch inverts x i when high, “1”
and does not invert when low, “0”.
When it is high, it also injects
a “1” into “c 0”.
In 3-bit two’s complement operations, overflow will occur when more than 3 bits are needed to represent
the result. This is equivalent to saying that overflow will occur when the sum or difference is over
+3 or under -4.
In hardware, one can detect overflow by checking the carries in and out of the most significant bit, that
is carries C2 and C3 . IfC2 ≠ C3 then an overflow has occurred. This is too hard to prove here. 1
What kind of a gate can check for inequality?
FIGURE 6 A controlled inverter circuit..
c 3
1. One can start by noting there can be no overflow unless the numbers have the same sign. Adding a positive and a
negative number gives a sum with a smaller magnitude than either input.
Lab2-4 SWITCHING CIRCUITS © J.Knight, January 23, 2002
y 2
FULL
ADDER
s 2
x 2
INVERT
CNTRL
c 2
y 1
FULL
ADDER
s 1
x 1
INVERT
CNTRL
c 1
y 0
FULL
ADDER
s 0
x 0
INVERT
CNTRL
A Controlled Inverter
To build a combination adder/subtracter, one needs a way to invert or not invert on command
FIGURE 5 A controlled inverter circuit..
Sub(H)/Add(L) Xi Zi 1 0 1
1 1 0
0 0 0
0 1 1
c2 c3 Ovf
1 0 1
1 1 0
0 0 0
0 1 1
X i
Sub(H)/Add(L) gate Z i = X i IF Sub(H)/Add(L) = 0
X i IF Sub(H)/Add(L) = 1
c 2
c 3
gate
Ovf
c 0

Prelab
(This must be prepared prior to the scheduled lab session. It will be checked near the start of the lab. It will
also be an appendix for your final report.)
3.0 Make a table of 5-bit two’s-complement numbers showing them opposite their decimal values. You
may put in a row of dots “. . .” to save writing, but show the top 3 numbers, the bottom 3 numbers, and
+2, +1, 0, -1 and -2.
3.1 Show how to calculate 3-bit two’s complement of numbers by inverting and adding 1. Use +3 , -1 and
-4 as examples. Decide if there is a 3-bit two’s complement of -4.
3.2 Do the following (a through d) arithmetic problems as a 3-bit binary adder/subtracter would do them.
Show how the carries propagate and how the overflow is calculated as is illustrated Fig. 7 (p. 5) for
the 4 bit subtraction of X - Y = (+5) - (-6).
(a) (+1) + (+2), (b) (+2) + (-2), (c) (-2) + (-3), (d) (+3) - (-3), (e) (-3) - (+3) .
FIGURE 7 Doing a 2’s complement subtract.
3.3 Complete the truth table for a generic full adder.
The three inputs are xi ,yi ,andci .
The two outputs are sum and carry, that is si and ci+1 Partial Truth Table for a Generic Full Adder
y i x i c i c i+1 s i
Not Equal Means Overflow 0 ≠ 1
(+5)
- (-6)
0
1
1
0
0
1
1
0
0
+
1
0
0
0
1
1
1
0
0
Carry
1
1
Subtract here means invert all bits here
Then the subtraction can be done as addition
(-5) 1 0 1
1
1
Initial 1 carry in, as part of
2’s complement calculation
Provided an extra 1 is added to the least significant bit.
Expression for
c i+1
1 1 1 1 1 yixici yixici 3.4 Obtain the equations for the generic full adder from the truth table.
3.5 Simplify the equations.
Hint 1: (This may or may not help you)
(a⊕b)c + ab = ac +bc+ab
Expression for
s i
0 0 0 0 0
0 0 1 0 1 y i x i c i
0 1 0 0 1 y ix ic i
0 1 1 1 0 y i x i c i
1 0 1 1 0 y i x i c i
-- -- -- -- -- ---- ----
The formula is proven below using Karnaugh maps. If you have not yet taken these maps you will
have to take it on faith for another week or so.
© J.Knight,January 23, ’02 SWITCHING CIRCUITS Lab2-5
c i+1
y i
FULL
ADDER
s i
x i
c i

Carleton University
FIGURE 8 The formula, proven below by Karnaugh maps, can slightly simplify the carry output.
ab
c
00 01 11 10
c
00 01 11 10
0
0
1 1 1
1 1
1 1
3.6 Take the simplified equations for the full-adder subcircuit you just derived
a) Draw a schematic from the minimal equations you derived.
3.7 What logic gate can function as a controlled inverter?
What gate can test two bits for equality?
3.8 Design a generic “invert control” unit that inverts the” x i” input when subtract is selected.
3.9 Design the circuit that detects overflow.
3.10 Draw a block diagram for the complete 3-bit adder/subtracter. Use blocks for the standard subcircuits
you designed in subsections 3.6 , 3.8 and 3.9 . The figure below gives an idea of what is wanted,.
However several necessary things are left out.
FIGURE 9 Partial block diagram of the adder/subtractor..
ab
1
1
1 1
3.11 You should have three types of blocks: full-adders, invert-control, and overflow detect.
Make sure you have a schematic of each type of generic block, with the gates drawn the way they will
appear in the lab.
This lab will be done with a computer simulation, so you will not run out of gates of any given type.
Lab2-6 SWITCHING CIRCUITS © J.Knight, January 23, 2002
ab
c
0
1
00 01 11 10
a⊕b (a⊕b)c (a⊕b)c + ab =
OVERFLOW
DETECT
SUB(H)/ADD(L)
SWITCH
OVF
c 3
y 2
FULL
ADDER
2
s 2
x 2
INVERT
CNTRL
2
c 2
1
FULL
ADDER
1
s 1
x 1
INVERT
CNTRL
1
y1 =
c 1
ab
c
0
1
00 01 11 10
1
1
1 1
ac +bc+ab
FULL
ADDER
0
s 0
x 0
INVERT
CNTRL
0
y0 LEAST
SIGNIFC
BIT
c 0