CARLETON UNIVERSITY - Department of Electronics at Carleton ...

CARLETON UNIVERSITY
DURATION: HOURS No. of Student:
Department Name & Course Number:
Course Instructor(s)
AUTHORIZED MEMORANDA
Final
EXAMINATION
April 24, 2002
Students MUST count the number of pages in this examination question paper before beginning to
write, and report any discrepancy immediately to a proctor. This question paper has 18 pages.
This examination paper May Not be taken from the examination room.
In addition to this question paper, students require: an examination booklet yes no x may request
a Scantron sheet yes no x
page 1 2 3 4 5 6 7 8 9 10 11 12
Name:
Number:
Signature:
3 398
Electronic Engineering 97.267A,B and C
Tom Ray and John Knight
Any notes; any non-communicating calculator.
Please write your answers on the examination paper. You may ask for a booklet if you need it.
Attempt all questions except do only one of questions 10 and 11.
1 Quickies (Please answer on question paper. Check on the right, if answer is in booklet.)
a) Draw a logic circuit which
2%
gives a “1” output if any twoout-of-three
inputs are “1”, but
not all three.
2% b) Which single variable change, if any, can cause a hazard (glitch) in the “Combinational
Logic” part of the circuit below in part c)_______A__________.
A has two paths, one inverted which reconverge at G
2%
c) What, if anything,
should you do about the
hazard in the logic of
this synchronous circuit,
if there is one?
CLK
X
Y
1D
C1
1D
C1
F
A
H
G
1D
A
B
K
Combinational Logic
C1
There is a hazard at G. To keep it from doing any damage, be sure the clock cycle is long
enough for it to die out before the next active clock edge.
© Tom Ray and John Knight
page 1 of 18

2%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
4%
2%
d) Many logic circuits run from a 5 volt power supply
and receive and send out logic signals which have a
logic “0” as 0 volts and a logic “1” as 5 volts. However
in this instance the input signals are not the usual.
C is 4.0 volts and B is 0.8 volts.
What logic level would you expect at A__0__
What logic level would you expect at R__1__
4 V is an adequate 1, 0.8 V is an adequate 0.
e) Simplify A+AB+BC+CD+DE+EF and don’t take too much space.
=A+B +BC+CD+DE+EF (x+xz=x+z)
=A+B +C+CD+DE+EF (x+xz=x+z)
=A+B +C+D+DE+EF (x+xz=x+z)
=A+B +C+D+E+EF (x+xz=x+z)
=A+B +C+D+E (x+xz=x)
f) Plot A·BC+BCDE on a Karnaugh map
A·BC is on both maps.
BCDE is on the E level (map only)
+5 volt power supply
© Tom Ray and John Knight April 14, 2003 page 2, of 18
+
C=4 volt
B=0.8 volt
AB\ CD AB\ CD
1 1 1 1
AB\ CD
R
E E
AB\
1 1
CD
1 1
1
A
1a)See
booklet
1b)See
booklet
1c)See
booklet

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
2 More Quickies
a) Change to a minimal sum of products form.
4%
2%
(A +BC)(A+EF)(ABC + DB )
(AEF + ABC)(ABC + DB) swap
AEFDB + ABC D2
Taking the dual here is a mark loser.
So is brute force multiplying out to 8 terms.
People who did so almost alwas made a mistake, and none got the minimal answer.
b) A minimized synchronous finite-state machine has
11 inputs,
14 outputs,
40 states in which 3 are equivalent,
and 129 logic gates.
How many flip-flops does it have?
_________6_______
6 flip-flops can give 2 6 states.
5 flip-flops can only give 32.
Pay no attantion to all that other confusing info.
© Tom Ray and John Knight April 14, 2003 page 3, of 18
2a)See
booklet
2b)See
booklet

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
3%
c) You have studied synchronous machines, asynchronous machines,
Mealy outputs and Moore outputs.
Which kind(s) of machine need race-free state assignments?
_________________________asynch____________________________
2%
Which kind(s) of machine respond the most quickly to input changes?
_______________________asynch______________________________
_______________________Mealy_____________________________
d) If 1101 is a two’s complement binary number, what is its value in decimal?
1101 = -2 3 *1 + ( 2 2 *1 + 2 1 *0 + 2 0 *1 )= -8+5=-3,
or 1101 0010
+1
0011 = 3dec
hence the original was -3.
© Tom Ray and John Knight April 14, 2003 page 4, of 18

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
3 MUX Logic and Hazards
e) Implement the function F using one or more of the MUXs shown. You may
use as many MUXs of any type as you need but:
- do not change the inputs, or the ordering of the inputs, on the symbols.
- do not use more hardware than needed for your method of implementation.
4%
abc
000
001
010
011
100
101
110
111
abc
ab
00
01
10
11
a b
bc
00
01
10
11
bc
f) Revise the equation for H, below, to make the function free of static hazards.
Give the minimal form that is still hazard free.
7%
F= ab + ac +ac
Not well covered in 2003
© Tom Ray and John Knight April 14, 2003 page 5, of 18
ac
00
01
10
11
a c
c
a
b
F= ab + ac +ac
1
0
1
1
1
0
1
0
b+c c
0
c
3a)See
booklet

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
Put the circles (loops) for the hazard free function including masks on the right hand
map.
Write the equation including masks below the map
Blanks
are zeros
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
H= AD +A B +BD + AC D + BC
B
B
B
H=A·B·D +AD+A·C·D +A·B·C
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
CD
AB 00
00 1
D
01 11 10
1 1 1
01 1 1
A
11 1
10 1 1 1
C
© Tom Ray and John Knight April 14, 2003 page 6, of 18
B
B
B

8%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
4 Races and Cycles
Do rough work on the top table.
The bottom table will be marked.
Arrows in the bottom table, which
are not part of the answer, will give
negative marks.
a) Indicate any cycles or races.
b) Indicate the path(s) from an
initial stable state by which
one enters the cycle or race.
c) Iftheracealonecouldcause
the circuit to malfunction write
BAD beside the arrow.
If the circuit should function
satisfactorily with the race,
writeOKbesidethearrow.
For a cycle write CY inside the
loop
we hope you have formed from
the arrows.
Present Next State, p + ,q +
State for inputs x,y
© Tom Ray and John Knight April 14, 2003 page 7, of 18
PQ
x,y
00
x,y
01
x,y
11
x,y
10
00 00 01 10 00
01 01 00 01 01
11 00 11 11 10
10 10 11 01 11
Present Next State, p + ,q +
State for inputs x,y
PQ
x,y
00
x,y
01
x,y
11
x,y
10
00
01
00
01
01
cy
00
10
01
00
01
11 00 11 11 10
cy
10 10 11 01 11
Present Next State, p + ,q +
State for inputs x,y
PQ
x,y
00
x,y
01
x,y
11
x,y
10
00 00 01 10 00
01 01 00 01 01
11 00 11 11 10
10 10 11 01 11
Present Next State, p + ,q +
State for inputs x,y
PQ
BAD
x,y
00
x,y
01
x,y
11
x,y
10
00
01
00
01
01
cy
00
10
01
00
01
11 00 11 11 10
cy
10 10 11 01 11
BAD
BAD
4) See
booklet

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
10%
5 Minimization of Multiple Outputs
Minimizethelogicsize.
a) Show your final circles on the lower map, rough work on the top maps.
b) Shade the circles that are common to two or more maps.
c) Write the logic equations under the maps.
YZ
WX 00
00
Z
01 11 10
1 1 1
YZ
WX 00
00 1
Z
01 11 10
1 1
YZ
WX 00
00
Z
01 11 10
1
01
11
W
10 d
1 1
1
1
1
X
01
11
W
10 d 1
X
01
11
W
10 1
1
1
1
1
1
1
Y
Y
Y
Map of F
Map of G
Map of H
3circlesto
get 1 bit
YZ
WX 00
00
Z
01 11 10
1 1 1
YZ
WX 00
00 1
Z
01 11 10
1 1
YZ
WX 00
00
Z
01 11 10
1
2circlesto
get 1 bit
01
11
W
10 d
1 1
1
1
1
X
01
11
W
10 d 1
X
01
11
W
10 1
1
1
1
1
1
1
X
Y
Y
Y
Can share
but extra
YZ
WX 00
00
Z
01 11 10
1 1 1
YZ
WX 00
00 1
Z
01 11 10
1 1
YZ
WX 00
00
Z
01 11 10
1
work to get
1 and 1
01
11
W
10 d
1 1
1
1
1
X
01
11
W
10 d 1
X
01
11
W
10 1
1
1
1
1
1
1
X
Alotof
work for a
d
YZ
WX 00
00
01
11
W
10 d
Y
Z
01 11 10
1 1 1
1 1 1
1 1
X
YZ
WX 00
00 1
01
11
W
10 d
Y
Z
01 11 10
1 1
1
X
YZ
WX 00
00
01
11
W
10 1
Y
Z
01 11 10
1
1 1 1
1 1 1
X
Y
Y
Y
YZ
WX 00
00
Z
01 11 10
1 1 1
YZ
WX 00
00 1
Z
01 11 10
1 1
YZ
WX 00
00
Z
01 11 10
1
01
11
W
10 d
1 1
1
1
1
X
01
11
W
10 d 1
X
01
11
W
10 1
1
1
1
1
1
1
X
A=WY
Y
Y
Y
B=WXZ
F=A+B+C+XY G=Z X+C
H=WX+A+B+C
C=W X Y Z
22 letters, 9 gates
© Tom Ray and John Knight April 14, 2003 page 8, of 18
X

8% 12%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
6 State Graph of a Synchronous Machine
Draw the state graph for a Moore machine which has one input X, and two out-
puts Y and Z:
Y=1 whenever the machine receives the sequence 1001.
Z=1 whenever the machine receives the sequence 0101.
The leftmost bit is received first.
Overlapped sequences are to be detected.
Y and Z are zero except for the single clock period after the appropriate sequence
is completed.
The machine starts at the RESET state.
Draw only the state graph
Use only the states provided below and do not change anything already given.
Got
Nothing
Got 0 Got 01 Got 010 Got 0101
Got
Nothing
Reset
YZ=00
0 Tom
YZ=00
0
1
1
Got 01011
Got 1
Got 10
Got 100
Got 1001
Anita
YZ=00
1
Got 11
0
YZ=00
0
Yana
YZ=00
1
Got 011
Yatish
0101
Got 10011
1001
1
1
1
0
Dick
YZ=00
Prize
YZ=10
© Tom Ray and John Knight April 14, 2003 page 9, of 18
0
0
Harry
YZ=00
Got 1000
1
Win
YZ=01
0
Got 01010
Got 0 of 0101
Got Nothing of 1001
Got 010
Got 10010
of 0101
Got 10 of 1001
1

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
.
Got
Nothing
Got 1
Got 10
Got 100
Got 1001
Got
Nothing
Reset
YZ=00
1
Anita
YZ=00
0
1
0
1
Got 0 Got 01 Got 010 Got 0101
Tom
YZ=00
Yatish
YZ=00
0
Yana
YZ=00
0
1
1
0
1
1
Dick
YZ=00
Prize
YZ=10
© Tom Ray and John Knight April 14, 2003 page 10, of 18
0
0
0
Harry
YZ=00
1
YZ=01
0
Win
1

8% 7%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
7 State Graph to Timing Diagram
CLK
I
State
z
For the state graph shown below:
a) Find one impossibility, circle it. and say what it is (in 10 words or less).
Answer__Two next states for the same input (I=1 in state B) is impossible.
b) Complete the timing diagram from the state graph. Show the present state and the output Z.
The impossibility in a) should not affect the answer.
C
I=0->z=1
I=1->z=0
I=0
I=1
R
z=0
I=0
I=0
I=1
I=1
B
I=0->z=0
I=1->z=1
© Tom Ray and John Knight April 14, 2003 page 11, of 18
I=1
I=0
D
z=1
I=1
R D C B A
I=0
A
z=1
States only change on the clock edge.
Check input just before the clock edge to calculate next state
Look inside state bubble for outputs information.
Only one input, so can just write 1, 0.
C 0
B
z=I
z=I
Another way of giving outputs
1
I=1
7)See
booklet

8%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
8 State Table to Circuit
Design a machine with minimum logic to implement the following state table.
Only the K-maps and the combinational circuits for the D inputs (DA and DB ) and Z are expected.
Do not change the states, state assignment or the operation of the machine
State
Q A Q B
.
State Q A + QB +
I=0 I=1
Output Z
I=0 I=1
R=0 0 V T 0 1
S=0 1 V T 0 0
T=1 1 R S 1 0
V=1 0 R S 0 0
State
Q A Q B
State Q A + QB +
I=0 I=1
Output Z
I=0 I=1
R=0 0 V=1 0 T =1 1 0 1
S=0 1 V=1 0 T=1 1 0 0
T=1 1 R=0 0 S=0 1 1 0
V=1 0 R=0 0 S=0 1 0 0
Q I
A QB 00
01
11
10
0 1
1
1
0
0
D A= Q A
1
1
0
0
D A =Q A +
Q I
A QB 00
01
11
10
0 1
DA Circuit DB Circuit
DA QA I DB QB 0
0
0
0
1
1
1
1
D B=Q B +
D B =I
QB QA Q I
A QB 00
01
11
10
Z Circuit
0 1
© Tom Ray and John Knight April 14, 2003 page 12, of 18
I
0
0
1
0
1
0
0
0
Z=Q A Q BI+ Q A Q BI
Z
8)See
booklet

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
9 State Reduction
In the state table below, and using a merge table, find which states, if any are equivalent.
Make a new state table with the minimum number of states
. Changed one next state of B and C from original exam to make the problem a little harder.
State Next State
I=0 I=1
Output
Z
R E A 1
A E B 0
B A B 0
C E C 0
D C R 0
E D R 0
A
B
C
D
E
A
B
C
D
E
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Different outputs
A B
E B
E C
E B
C R
E B
D R
E B
E C
A B
C R
A B
D R
A B
C R
E R
D R
E R
D R
C R
R A B C D
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
A B
E C
E C
E B
C R
E B
D R
E B
E C
A B
C R
A B
D R
A B
C R
E R
D R
E R
D R
C R
R A B C D
To merge states
Must have the same output.
Must have the same next states
However
They only have to be the same
after all the mergers.
Setting up the merge table
BandAcan merge
only if (A and E)
and (B andC))
are merged.
AandEcan merge
only if (B and R)
and (D and E)
are merged
BandRhave
different outputs!
Thus DandE
are irrelevant
© Tom Ray and John Knight April 14, 2003 page 13, of 18

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
A B
E C
E C
E B
C R
E B
D R
E B
E C
A B
C R
A B
D R
A B
C R
E R
D R
E R
D R
C R
R A B C D
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
A B
E C
E C
E B
C R
E B
D R
E B
E C
A B
C R
A B
D R
A B
C R
E R
D R
E R
D R
C R
R A B C D
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
Z=0
Z=1
A B
E C
E C
E B
C R
E B
D R
E B
E C
A B
C R
A B
D R
A B
C R
E R
D R
E R
D R
C R
R A B C D
Gray squares
have been
eliminated as
merger candidates
on previous
iteration
D C
E C
E D
D C
© Tom Ray and John Knight April 14, 2003 page 14, of 18
E
Three way
merge

Carleton University Electronics, 97.267A, B and C Final April 24, 2002
C will merge with D, C with E and E with D.
Thus all three can merge into CDE..
Review
State Next State
I=0 I=1
OutputZ
R CDE A 1
A CDE B 0
B R B 0
CDE CDE R 0
Assigning Bit-Patterns to Difficult State Graphs By Adding States
A difficult state graph
A B K
D
R
Triangular states connections
like ADR, can never all differ
by only one bit
Here A and R could not be
made adjacent because
of the triangle.
00
01
11
10
0 1
A B
D R
Assigning Bit-Patterns to States Using Flow-Through States.
A difficult state graph
x,y=1,1
x,y=0,d
A B K
D
xy=1,1
R
Triangular connections
x,y=1,1
K
A B K
© Tom Ray and John Knight April 14, 2003 page 15, of 18
D
α
x,y=0,d
A B K
D
x,y=1,1
R
R
Add a temporary
state α to eliminate
the triangle
Since x,y=1,1 sends both R and
D to A, let R flow through D.
(D acts as a transient state)
00
01
11
10
The new state
assignment
without races
00
01
11
10
0 1
A D
α R
B
0 1
A
B K
R
D
K
Race free
Assignment

12%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
10 Race-Free State Assignment. (Do either question 10 or 11 but not both.)
For the following state table, revise the table and select a race-free assignment
.Do not change the machine any more than necessary.
Keep R as state 001.
Do not increase the number of rows in the table. Do not merge states.
Enter all of your answers below --- means “don’t care”
.
State Next
State,
Input
XY=00
Next
State,
Input
XY=01
Next
State,
Input
XY=11
Next
State,
Input
XY=10
A --- A A B
B E --- --- B
C C A C B
D C D R D
E E D C E
R NotC
Allowed
A R D
State Next
State,
Input
XY=00
Next
State,
Input
XY=01
Next
State,
Input
XY=11
Next
State,
Input
XY=10
A --- A A B
B E --- --- B
C C A C B
D C D R D
E E D C E
R C A R D
B
C
A R
© Tom Ray and John Knight April 14, 2003 page 16, of 18
C
Assign states
on map.
Circle stable states
Identify allowed
state transitions
Make graph
of allowed
transitions
B
C
E
A R
C
D
Trytogetridof
triangles.
D
B E
Use transient states
to avoid races.
00
01
11
10
0 1
A
R
C D
B E

12%
.025%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
Answer: Fill in the state table. Use letters to represent states, as above.
Write your state assignmnt in a table (K-map).
State Next State,
Input
XY=00
Next State,
Input
XY=01
Next State,
Input
XY=11
Next State,
Input
XY=10
A A=000 A=000 C=010
B E=111 C=010 B=110
C C=010 A=000 C=010 B=110
D D=011 D=011 R=001 D=011
E E=111 D=011 B=110 E=111
R C=010 A=000 R=001 D=011
11 Race-Free State Assignment. (Do either question 10 or 11 but not both.)
A master-slave D flip-flop can be made differently than was shown in the notes.
a) Find the best place(s) to break the circuit for analyze. Try to use the minimum
number of breaks.
z
b) Label the next-state/state variables across breaks like this
c) Derive the equations relating the variable on the left side of the break to the inputs and the
variables on the right hand side of the break. Make appropriate circuit simplifications graphically.
+
Z
C
D
C
D
E
N
M
F
E
N
M
F
C
m M +
N
C
© Tom Ray and John Knight April 14, 2003 page 17, of 18
C
M
N
C
V
P
W
V
P
W
q +
00
01
11
10
0 1
A R
C D
B E
Q
Q P
Q
Q P

.025%
Carleton University Electronics, 97.267A, B and C Final April 24, 2002
C
D
C
D
E
N
M
F
E=C+D
N
M
F=DC
m +
C
N=M+DC
C
M
N
C
M
When 2002 is written in binary, what will the least significant bit be?_______
Have a good summer! Even numbers end in 0.
© Tom Ray and John Knight April 14, 2003 page 18, of 18
C
V
P
W
V=M+C
Q
W=CN
Q
Q P
P
q +
Q
P=Q+W=Q+CN
m+=(M + F)(C + D) = (M + DC)(C + D) = MC+ MD + DC = MC + DC (concensus)
q + = (Q+W)(C+M) = (Q+CN)(C+M) = QC+QM+CNM) = QC+QM+C(M+DC)M
=QC+QM+CM=QC+CM (concensus)
Note