Laboratory 4 A MIDI Interface - Department of Electronics at Carleton ...

CARLETON UNIVERSITY
Deparment of Electronics
ELEC 2607 Switching Circuits March 1, ’06
Laboratory 4 A MIDI Interface
Overview
MIDI is the name for a digital interface used in electronic music. It might be used between a digital keyboard
and a synthesizer or between a keyboard and a PC running a music composition program, like Cake-
Walk or Gigastudio. MIDI is a serial interface, the bits come in one after the other. The high-level view of
a MIDI interface is shown below.
FIGURE 4.1
OPTO
ISOLATER
serial
in Serial
to
Parallel
Receiver
parallel
out
DATAVALID
The opto-isolator changes the electrical signal to light and back again. It keeps the rest
of the interface from burning out if the MIDI input gets plugged into 120 V by someone with
strong wrists and limited technical knowledge.
The Serial-to-Parallel Receiver changes the 10-bit serial-data word from the keyboard ?
into an 8-bit parallel data word which is then sent to the computer. This is what you will design.
The 10 bit serial word has a start and stop bit which are removed for the 8 bits parallel
output.
This receiver captures 8 bits as they come in serially one after the other. A group of bits may start at any
time. The receiver waits until all 8 bits are collected. Then it sends them out in parallel some other instrument
like a mixer or computer. It makes the DATAVALID line true when the word has been completely received and is
available for the computer to read.
Each 8-bit word has a musical meaning. The first word is called the STATUS word, which is followed by
zero, one or two DATA words, as appropriate for the status word. Table. 4.1 shows some commands. The
Table 4.1Some MIDI commands applicable to keyboard interfaces.
STATUS DATA-1 DATA-2 Description
FF -none- -none- Reset the MIDI system
80 Note -none- Note off
© J.Knight, March 1, ’06 SWITCHING CIRCUITS MIDI-1
S ynth

Carleton University Overview
words STATUS, DATA-1 and DATA-2 are interpreted in software. If you are interested in interpreting MIDI
commands you might try to continue this work as a final-year project. This lab will look only at the hardware
part of the interface.
The Serial Signal
Table 4.1Some MIDI commands applicable to keyboard interfaces.
STATUS DATA-1 DATA-2 Description
90 Note Velocity Turn on Note in DATA-1 with key Velocity in DATA-2
D0 Pressure -none- Change key pressure of the current note, in mid-note.
The keyboard will send out a word made up of 10 bits sent serially one after the other. The idle time between
words is of indefinite length.
FIGURE 4.2 A typical MIDI signal showing three words.
FIGURE 4.3 The protocol used by MIDI equipment. The data bits are drawn as both 1 and 0 since they
may be either.
IDLE
10 BIT WORD
INDEFINITE
IDLE
TIME
10 BIT WORD
10 BIT WORD
START
BIT
LEAST
SIGNIFC
BIT
32.0 µs
0.320 ms
8 DATA BITS
MOST
SIGNIFC
BIT
IDLE: The signal is always “1” when idle.
START BIT: The signal always has one low (0) bit before the 8 data bits start. This tells the interface to
start listening.
DATA BITS: 8 data bits follow the start bit. Any individual bit may be “1” or “0.” Table. 4.1, shows
STATUS words always start with a “1”, DATA -1 and DATA-2 words always start with a “0.”
STOP BIT: The STOP BIT follows the last data bit and is always “1”. It is really the start of the next
idle period. The next start bit may come immediately after the stop bit, or the signal may be
idle for years.
Sampling the Individual Serial Bits
Each bit is transmitted for 32.0 µs. Your circuit will sample each bit in the
MIDI signal with a SAMPLE signal which will have a 4.0 µs period.The MIDI signal
will be sampled during the 4.0µs that SAMPLE is high.
One would like to sample the MIDI signal in the middle of each bit where the
data is stable. This does not happen naturally. You must design your circuit so the
downward edge of the start bit starts the SAMPLE signal. However SAMPLE stays
IDLE TIME WAS ZERO HERE
MIDI-2 SWITCHING CIRCUITS © J.Knight, March 1, ’06
STOP
BIT
INDEFINITE
IDLE
TIME
32.0 µs
SAMPLE
IDLE
time
NEXT
START
BIT
4.0 µs
time

low for ~14µs so that its high part will come near the centre of the MIDI bit. Sample will then go high for 4.0µs
during which time the MIDI signal is sampled. Then SAMPLE goes low for 28µs and comes up again in the
middle of the next MIDI bit. SAMPLE is periodic so all ten bits will also be sampled near their middles. Then
SAMPLE goes low and waits for the next START BIT.
FIGURE 4.4 The detailed timing relations between the MIDI signal and the SAMPLE signal.
~14.0µs
Idle period
Start of
10-bit
MIDI word
FIGURE 4.5 This shows the falling edge of the START bit (at the big black down-arrow) for three consecutive
Midi instructions. Approximately 14µs after this edge (3 or 4 clock-cycles) , the SAMPLE signal
starts. It then goes on and samples all 10 bits near the middle where they are stable. After 10 bits
SAMPLE goes low and stays low until restarted by the next START bit.
SAMPLE
MIDI SIGNAL
32.0µs
32.0µs
4.0µs
Design Problem for This Lab
28.0µs
SAMPLE
MIDI SIGNAL
In this lab, you will design the logical part of the MIDI interface, the serial-to-parallel receiver. You will
draw your circuit on the screen, simulate the results, and download it to a complex logic device (CPLD).
The Receiver
Signals which are restricted so they physically cannot change at the same time as the active clock edge
are called synchronous. If they might be able to change on that clock edge, they are called asynchronous.
The receiver input is called asynchronous because the start of a new word (the start of the START BIT)
at the MIDI input (SI) does not have a known relationship with the receiver clock. Each new word in the SI signal
may start at a random or asynchronous time.
FIGURE 4.6 Diagram showing receiver inputs and outputs
MIDI input
SI
CLK
4.0µs period
RST
DATA0
DATA1
DATA2
DATA3
The receiver has the following input and output signals
32
32
SERIAL-TO PARALLEL
RECEIVER
FOR AN
ASYNCHRONOUS INPUT
DATA4
Idle period
End of
10-bit
MIDI word
© J.Knight,March 1, ’06 SWITCHING CIRCUITS MIDI-3
DATA5
DATA6
DATA7
DATA-VALID
most significant bit

Carleton University For The Prelab, Implement This Design
SI Serial Input.....The received MIDI signal
CLK This is supplied externally, say from a PC, and has a period of 4.0 µs, 8 times the signal bit
speed. CLK is not synchronized with SI. The rising/falling edges of CLK are at arbitrary
times with respect to the rising/falling edges of SI.
The CLK is sacred. It must go to the clock pin of all counters and flip-flops. It must not go
through gates or be delayed in any way. All flip-flops must clock at the same time. If the
clock reaches them at different times it is called clock skew, which causes many problems
RST Asynchronous reset; this is used for initializing the circuit on power-up. It is also used in
factories for automatic testing. It should go to the CLR connection 1 on every flip-flop. It
must not be used for things like clearing a counter at the end of its count.
DATA0...DATA7 The received 8-bit data word. DATA0 is the least significant bit.
DATAVALID DATAVALID = 0 whenever the data on the parallel output pins may not represent the last serial
word received, that is the last word may be corrupted by new incoming data.
DATAVALID = 1 after the STOP BIT has been received, and the data may be read out in parallel
by the computer. It stays 1 until new serial input data changes the parallel output lines.
For The Prelab, Implement This Design
Modular Design
The interface can be divided into modules such as shown on the next page. We strongly encourage you to
use modular design. Enter and test each part individually.
Suggested modules and their input and output signals are shown. If you use these modules and the same
wire names, you can use the test input files supplied.
SI
CLK
ACTIVE
SAMPLE
DATAVALID
QUIT
Waveforms
Consider the signals shown above. Also refer to the block diagram Fig. 4.7. The CLK goes to all flipflops
all the time. The SAMPLE signal enables certain flip-flops to effectively clock at a slower rate without
causing clock skew. Placing a gate in the clock line could also do this, but this would cause clock skew and
false clock edges, horrors which you will learn about in ELEC 3500.
1. Xilinx library flip-flops use CLR for asynchronous reset and R for synchronous reset.
FIGURE 4.8
MIDI-4 SWITCHING CIRCUITS © J.Knight, March 1, ’06

SI
Serial In
RST
CLK
The flip-flops inside the CONTROL and SER2PAR blocks change only when enabled by SAMPLE.
Signals in STRT_STP and DIVBY8 respond at the 40 µs clock rate.
The ACTIVE signal
DATAVALID (goes high on the 1st SAMPLE pulse, and goes low after 10)
STRT_STP
DIVBY8
ACTIVE SAMPLE
RST
QUIT
SAMPLE
SI
SER2PAR
RST
DATAVALID
ACTIVE goes high after the START BIT in SI goes low. It stays high until after half way through the
STOP BIT. Thus ACTIVE tells when there is a serial signal coming in.
ACTIVE going high starts the DIVBY8 counter. This counts 4 CLK cycles and then sends out the SAM-
PLE pulse.The sample pulse is one clock-cycle wide in the middle of each bit of SI. SAMPLE always comes in
the middle of each bit where SI is stable. Not at the edges where SI is changing.
The DATAVALID signal
DATAVALID is fed back from the CONTROL block into STRT_STP to turn off ACTIVE at the end of
each 10 bit word.
To initially lower DATAVALID when a word starts to be received, use the first SAMPLE pulse.
The SAMPLE pulses start 4 clk cycles after ACTIVE goes true.
After sending out the first SAMPLE pulse, the DIVBY8 counter now counts 8 clock cycles and sends out another
SAMPLE pulse. The DIVBY8 counter continues as long as ACTIVE is true.
The CONTROL block counts the number of bits:
It knows the last data bit is sampled, after 9 SAMPLE pulses (the counter reads 9).
It knows the STOP BIT is sampled, after 10 SAMPLE pulses (the counter reads 0).
After DATAVALID becomes true, the ACTIVE signal is turned off.
The QUIT signal
After 9 SAMPLE pulses the QUIT signal tells the SER2PAR block that all the data-bits are read, and it
should stop collecting data. Note the difference between all the data-bits, and all the data-bits plus the stop bit.
© J.Knight,March 1, ’06 SWITCHING CIRCUITS MIDI-5
RST
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
CONTROL
QUIT
QUIT receiving new data, only the STOP or idle bits are coming in.
DATAVALID
Read the 8 DATAx lines
only if DATAVALID=1.
FIGURE 4.7 Block diagram showing suggested block names and wire (net) names for the MIDI
interface.You may have to make minor modifications to this, or to the preloaded file.

Carleton University Description of the Blocks
Description of the Blocks
The STRT_STP Block
Refer to the timing diagram Fig. 4.9. Note particularly:
Region B is shaded .
Region C is shaded .
Note the values of SI, DATAVALID and ACTIVE in the regions A, B, and C.
Region C is when SI is not active, that is idle. See Fig. 4.4.
When Region A is where ACTIVE starts up, but before DATAVALID goes false (low).
Design the circuit to generate the ACTIVE signal from SI and DATAVALID.
FIGURE 4.9 Timing used to generate the circuit for STRT_STP
SI
DATAVALID
0
1
0
ACTIVE
B
C
A
Complete truth table, Karnaugh map and schematic for STRT_STP. With proper use of don’t cares, you will
need only one 2-input gate. Don’t cares come from impossible inputs; why cannot DATAVALID stay 0 in region
C?
DIVBY8
This circuit basically divides the clock by 8 to get a 32.0µs time base, which is used to generate a single
4µs pulse every 32.0µs..
ACTIVE
CE
CLK
RST
Q0
Q1
Q2
to where?
CLR = ASYNCHRONOUS RESET
CE = CHIP INPUT ENABLE
CARRY OUT “TC” ON 7 COUNT
Care must be taken to only sample the SI signal when it is stable. One way is to read SI in the middle of
each bit. Since CLK is 8 times the bit rate of SI, this can be done sampling the first bit after 4 CLK pulses and
MIDI-6 SWITCHING CIRCUITS © J.Knight, March 1, ’06
D
C
CE
D
C
CE
D
C
CE
Q
CLR
Q
CLR
Q
CLR
TC
Q0
Q1
Q2
stop
bit
Q0 + = ( Q0 )·CE + Q0·CE
On the flip-flops
CE = Clock Enable (Chip Enable)
The Q output will not change unless
CE is high.
1
1
FIGURE 4.10
A 3-bit binary counter you
will need to modify
Q1 + =( Q0⊕Q1)·CE + Q1·CE
fdce in the Xilinx libraries
Use fdc if CE is not needed.
Q2 + = (Q2⊕(Q1·Q0)·CE + Q2·CE
Where should ACTIVE be placed in these
equations?

then every 8 pulses thereafter. A counter which counts up to 8, can do the proper frequency division.
The most significant bit Q2 will change at 1/8 of the clock frequency.
A typical binary counters is shown in Fig. 4.10. This counter has an output called TC (terminal count). It
gives a pulse, one clock cycle wide, every 8 clock cycles (every count of 7). TC was designed to trigger another
counter to allow the two counters to count to 64. If you are counting every clock cycle you do not need CE.
The circuit shown can be modified to give an output after 4 clock cycles (a count of 3) and every 8 cycles
thereafter. It should also be modified so the count goes to zero when ACTIVE goes low. This should be done
synchronously, on a clock edge, by feeding zeros to the D inputs. Don’t even think about using the asynchronous
CLR for this. This counter is a starting point for DIVBY8, but some of the names and circuitry are different.
For example TC and GoToZero will need to be changed. It may help to look at the state graph on p.10.
The CONTROL Block
This circuit counts the SAMPLE pulses and generates two signals from the count:
1) The QUIT signal tells the serial-to-parallel shift-register that all the data-bits are read, and it should stop
shifting. Note there is a difference between all the data-bits, and all the data-bits plus the stop bit.
2) The DATAVALID signal turns off ACTIVE.
DATAVALID must be 1 at the very start of the START-BIT in SI to initiate raising the ACTIVE signal.
This circuit needs to count 10 sample pulses, start, 8 data bits and stop. This is a decimal counter. Such a
counter has Q0, Q1 and Q2 exactly like the previous binary counter. However Q3 must be added. Note the state
after nine is not ten, but zero. If you have designed the previous counter to synchronously go to zero on a count
of three, then you know how to make this counter go to zero synchronously after a count of nine.
Note the counter chip enable (CE) holds the counter at its old count until enabled by SAMPLE. Hence use
flip-flops with chip-enable (Xilinx cell fdce) in this design.
Alternate CONTROL Block
One does not need to design a separate counter. The shift register described in the SER2PAR block can
keep track of the number of bits coming in. Use an extra D flip-flop and a gate to clear or set every flip-flop on
the 11th SAMPLE pulse.You must be able to tell when the input SI has finished, no matter what the data is.
RST
CLK
SI
DATAVALID
STRT_STP
FIGURE 4.11
The SER2PAR Block
You need to design an 8-bit serial-in/parallel-out
shift register in which you can serially
shift in the data bit values as they are read. Run
the flip-flops from the 4ms clock, but use the
CE (chip enable) inputs so they are effectively
DIVBY8
ACTIVE SAMPLE
RST
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
© J.Knight,March 1, ’06 SWITCHING CIRCUITS MIDI-7
SI
DATAVALID
SER2PAR2
DATA0 should be the 1st bit after START
RST
D
C
CLR
Q=data4
D
C
CLR
Q=Data3
D
C
CLR
Q-Data2
D
C
CLR
DATAVALID
Q=Data1
D
C
CLR
Q=Data0

Carleton University In The Lab.
clocked at the SAMPLE rate. A basic shift register shifts all bits right one flip flop every clock cycle, and is illustrated.
It does not use the CE, but you should.
In The Lab.
After you have designed the circuit, you will enter it graphically into the
computer as schematic diagrams. Instructions for doing this will be given in the
laboratory. After the circuit is entered, you will simulate it to check its operation.
While the blocks are individually simple, connecting the whole circuit at
once will make debugging difficult. Implement the above blocks one at a time.
Test fixture files are available to help you simulate the individual blocks. There is
also a test file to simulate the whole MIDI interface.
By the end of the first lab period you should aim to have entered three of
the blocks. Simulating and debugging will be slow. Do not leave too much for
the second period.
Displaying Waveforms
The test fixture file can do a lot to help you check your circuit. There are
three waveforms, not in your circuit, which should be displayed.
StudNumb displays your student number for comparison with the midi data.
startguide displays a pulse during the start bit to make it easy to find.
serialin displays the serial input data as an integer.
data displays the parallel output data as an integer, with DATA0 as the least
significant bit.
The Test for the Complete Circuit
After you have run the simulation file on the full MIDI schematic, you should run it with your own data.
The test files are written in Verilog, a language for describing and simulating digital circuits. You will
use Verilog next year in ELEC3500.
All Verilog instructions end in semicolons. If there is no “;” the instruction is continued on the next line.
Comments start with //.
In the midi file, the 10 values of SI which make up the MIDI word are written out serially
as in Fig. 4.12 The values of SI are set. The #32 indicates a 32 µs delay before the next
change. Thus both boxes on the right give the pulse shown below them. Writing the #32 between
the lines makes it clearer where the delay is, but takes more space.
The data word shown Fig. 4.12 is 0 0 1 1 0 0 0 1 1 1, the start and stop bits are underlined.
// Start bit
SI=0; startguide=1;
#32; startguide=0;
// 8 Data bits
SI=0;
#32;
SI=1;
#32;
SI=1;
#32;
SI=0;
#32;
SI=0;
#32;
SI=0;
#32;
SI=1;
#32;
SI=1;
#32;
// Stop Bit
SI=1;
#90;
Your student number, or your partners, is used as data in the midi test_top.tf test fixture file.
integer StudNumb;
// ENTER YOUR STUDENT NUMBER HERE.
//------------------------------initial
StudNumb = 312153;
//-------------------------------
The Verilog program will translate it into binary, and use the 8 least significant bits as test data.
FIGURE 4.12
Part of the test file
SI = 0;
#32;
SI = 1;
#32;
SI = 0;
SI = 0;
#32 SI = 1;
#32 SI=0
MIDI-8 SWITCHING CIRCUITS © J.Knight, March 1, ’06
SI
32 64

SI
CLK
In the simulation the incoming midi bits are exactly 32µs long and the receiver clock is exactly 4µs. Normally
the transmitters idea of a µs is not the same as the receivers.One will be a little faster. If the clock period
were say 2.4 µs the SAMPLE pulse would not be in the right place to sample the final bits.
Changes to the midi test_top.tf (test_top2.tf) file
ACTIVE
SAMPLE
SI
CLK
ACTIVE
1) Change the part of the file shown in Fig. 4.12 to make the data word to 0110011001
2) Make sure the signal StudNumb is on your list of signals to be displayed.
Run the simulation with the default StudNumb=312153.
Then enter your student number in midi_test and rerun the simulation. 2
3) (Optional) Making the interface fail
Find, in test_top.tf, where the clock is generated and change the period to 4.1µs. Note the delay is a
half period. If you reduce the clock speed, the SAMPLE pluses will be further apart, but the SI bits will
come in at the same rate. Their speed is controlled by a different clock.
SAMPLE
Increase the delay in 0.1µs steps until you lose the final data bit. The timescale in the program will not
accept any finer resolution than 0.1µs.
The test fixture has been set up to print, in the log file, the serial-in parallel-out values for the data, albeit
in hexadecimal. It is easy to see if they are not the same.
Your Report
The marker will not believe that you intuitively know how the Midi interface works. You must explain,
at a high level, the function of the complete interface and the individual blocks. For example, could you not
give a better explaination of the ser2par block than is in the lab sheet.
Your design and design methods should be included. Most peoples designs will follow the prelab outline.
Brag about any changes you made, particularly if you think they are an improvement.
Your report should be coherent, and not jump over design derivations. Put in your schematics and your
final simulation. The circuits should agree with those you actually used.
2. If 312153 is your student number, use your lab partners number.
FIGURE 4.13showing
where the data bits
are sampled
FIGURE 4.14 With a
slower clock, the
last bit is skipped.
© J.Knight,March 1, ’06 SWITCHING CIRCUITS MIDI-9

Carleton University Your Report
Testing and implementation are important. You should neatly highlight and write comments on the
waveforms. It is very hard for someone to make sense of simulation waveforms if they do not know what is being
simulated. You must explain what the waveforms mean.
Common reasons for losing marks in MIDI reports
The author of each section is not identified at the top of each section.
The report uses two much unexplained jargon. For a reference level, assume your report will be used a
crutch for a student doing the lab next year. He/she should be able to understand it.
The paragraphs or sentences do not make sense. Example from a recent report, “Since SI is asynchronous,
the SI data is input when the data is low.”
Not describing the modifications that had to be done to modules.
Not describing the final simulation. This is the test that your circuit works. State how you know your circuit
works. Be sure to write short neat comments on the waveform printout.
We repeat! Annotate your waveforms.
Leaving out sections.
Copying the sections verbatim from the laboratory write-up.
Copying pictures from the lab sheet and not acknowledging them.
Not attaching the prelab as an appendix.
Not placing your names on the schematics.
Copying a last years report. The changes give this away easily. Plagiarism is a major offense.
FIGURE 4.15 State graphs for DIVBY8 and CONTROL
6
7
5
0
ACTIVE
4
1
2
3
sample
9
QUIT
MIDI-10 SWITCHING CIRCUITS © J.Knight, March 1, ’06
s
8
s
7
s
s
6
0
QUIT
DataValid
s
5
s
s = sample
4
1
2
3
s
s
s