Freescale PowerPoint Template

August, 2010 

Freescale Roadmap for Communications Processors 

Built on Power Architecture ® Technology 

NET-F0425 

Jeffrey Ho 

Technical Marketing 

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., 

Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink 

and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 

TM

►Market Trends and Impact on Processor 

Architectures 

►Freescale – Leader in Embedded Computing 

►Power Architecture ® Technology Roadmap 

►Multicore Leadership Solutions 

►Enablement 

►Q&A 



and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2 

Agenda 

TM

Smart, Efficient Networking Backbone for Trusted Connections 

Tablets 

eReaders 

Smartbooks 

Mobile Devices 

Smartphone 

Residential Gateway 

Smart Meter 

Factory HMI 

Medical Devices 

Smart Energy Grid 

Telematics 

Auto Infotainment 

Machine to Machine 




Energy Gateways 

Human Collaboration 

Video/IP Phones 

Wireless Access Pomit 

Touchscreen Printers 

Mobile Computing 

Desktop Computing 

TM

Multicore Solutions in the Heart of Our Connected World 

Growth Relative to 2008=1 

The 

Gap 

“The Gap” 

Exponentially increasing performance 

demands cannot be met by 

Moore’s Law alone. 




►Stagnating CapEx drives increased 

CapEx efficiency 

►Ability to deliver „more services‟ at 

lower CapEx… 

►Service density and data deluge of 

network traffic drives significant 

opportunities in Multicore SoC 

►Freescale closes “The Gap” with a 

“balanced, application-driven 

architecture”: 

• Smart multicore devices 

• Targeted application acceleration 

• Hardware assisted virtualization 

• Aggressive process technology 

• Extensive ecosystem and VortiQa 

multicore optimized software 

TM

Embedded Multicore Architectural Leadership 

Applications, Software and Ease-of-Use 

driving definition of multicore SoC architecture 

– not the other way around… 

Processor 

Cores 

Virtualization 

High Speed 

Interfaces 

Accelerators 




Services 

Applications 

Network 

TM


Architectures 




►Enablement 

►Q&A 




Agenda 

TM

Freescale – Leader in Embedded Processors 

Best performance at a given power for embedded & infrastructure solutions 

► Continued innovation in hardware architectures 

• QorIQ Platforms: Broadest scalable family of processors in the market 

• Evolution from PowerQUICC family 

• Dual core @ 800 MHz at < 5 Watts 

• Eight cores @ 1.5 GHz/core at 30 Watts 

• StarCore DSP solutions 

• Up to 1.0 GHz in 3-6 core configurations with advanced accelerators 

• Industry leading integration and communication engines 

► Increasing software investment 

• Optimized multicore solutions 

• Hybrid software simulation environment and debug tools 

• Production-ready software with VortiQa solutions 

• Fast time to market 

• Simplified migration to multicore architecture 

• More flexibility to create a uniquely differentiated product 

► 45nm high-performance technology in production 




2-8 Core 

CPU 

1-2 Core 

CPU 

4-6 Core 

DSP 

QorIQ P4080 

PowerQUICC MPC8572 

QorIQ P2020 

PowerQUICC MPC837x 

MSC8144 DSP MSC8154 

MSC8156 DSP 

Service Provider Enterprise Consumer Access 

Industrial and Aerospace 

TM

Power.org : IBM and Freescale Collaboration on Power 

Architecture ® Technology 

► Power Architecture Advisory Council – PAAC - IBM and Freescale 

• Maintain integrity of the ISA over its evolution – open architecture 

• Collaboration on technology innovations 

► Recent Innovations - ISA 2.04/2.05/2.06 

• Added support for multicore, virtualization and hypervisor 

• Additional instructions: Write and pre-fetch instruction for improved performance 

► Technical Working Groups 

• Common debug methodology – single industry-wide approach 

• Hypervisor 

Full virtual CPU virtualization 

Para-virtualization, API H-call interface for embedded PAPR 

• Simulation modeling – framework for compatibility between simulation tools 

• ABI – Application Binary Interface - Ecosystem enablement 

► Future Innovations within the Architecture 

• Power management 

• Virtual CPU/Hypervisor 

• 64-bit Architecture 

• Multicore 




TM 

TM

Application-Driven, Balanced Multicore Architecture 

“Intelligence is the ability to avoid doing 

work, yet getting the work done.” 

- Linus Torvalds 

Purpose of Balanced Architecture is to 

make the cores/multicore SoC more 

productive. Simultaneously, enabling a 

lower power & lower complexity software 

with very high networking performance 

Increasing the number of cores does 

not guarantee improved performance 

► Distributing packets to different cores 

► Parse and classify, load-steering, network 

accelerators (Crypto, DPI, etc.) and 

multi-level prioritized queuing 

► Maintaining flow order 

► Shared data structures 

Handles over-the-top traffic & services 

► Bandwidth-intensive multimedia and mobile traffic 

affected by social patterns or new service creation 

(Facebook, Telepresence, Skype) 

Cores 

Congestion 

Mgmt 

Policing 

Stash 

Context 




Virtualization 

Network 

Interfaces 

QorIQ P4 Platform DPAA 

Parse 

FMan 

QMan BMan 

Manage 

Work Q 

Accelerators 

Classify 

Enqueue 

Steer 

TM


Architectures 




►Enablement 

►Q&A 




Agenda 

TM

Power Architecture ® Cores Portfolio 

► 

PowerQuicc, 

QorIQ P2/P1 

e500 v2 

QorIQ P3/P4 

e500mc 

QorIQ P5 

e5500 

► 32b PPC-E 

► OOO, Dual-Issue, 7-stage pipeline 

► Support SPE and EFPU 

► Designed for Shared Bus, supports SC/DC 




Core Roadmap 

► e500 mc plus additional capabilities: 

► 64b ISA2.06 

► 36 bit addressing (64GB) per process 

► Full speed FPU 

► Extended Branch Predictor for 64b mode 

► Additional Integer/FP instructions 

► Support 512KB BS L2 

► Supports 32-bit mode for software legacy 

► Support Hypervisor/ Trust Architecture (secure 

Boot, anti-Tamper/Detection 

► e500 v2 plus additional capabilities: 

► Support Hypervisor/ Trust Architecture (secure Boot, anti-Tamper/Detection 

► Support DP FPU (classic), decorated L/S instructions 

► Support 128K/256K BS L2, 64 entries MMU TLB variable size, 64B CL 

► Designed for CoreNet Coherency Fabric, double snoop BW 

TM

Decreasing Power 

Increasing Performance 

1x 

High Performance 

within Embedded 

Power Budget of 

30W 

Performance at 

Reasonable Power 

Value Priced 

for Power/Performance 

Applications 

Power Sensitive 

Applications 

e600 +Soc 

PowerQUICC III 

PowerQUICC II Pro 

PowerQUICC II 

PowerQUICC I 




Roadmap: Freescale Processors Built on 

Power Architecture ® Technology 

Step Function Performance Increase 

3x 

First Generation: 45nm 

QorIQ – P5 

P5020/P5010 

e5500 

QorIQ – P4 

P4080/P4040 

e500mc 

QorIQ – P3 

P3041 

e500mc 

QorIQ – P2 

P2040 

e500mc 

P2020/P2011 

e500v2 

QorIQ – P1 

P1020/P1021/P1022 

e500v2 

Increasing Performance 

Enhanced Virtualization Support 

Next Generation 

Higher core frequency 

Increasing # of cores 

More software friendly 

architecture, enhanced 

virtualization support 

Heterogeneous cores, 

DSP + Power cores 

Application accelerators 

Next process technology 

node 

Continuous enhancement of application performance 

TM

► Next-Generation 64-bit core architecture for higher 

performance, computational intensive applications 

• 64-bit ISA support (Power Architecture v2.06 compliant) 

• Increased addressable memory space 

• Scalable up to 2.5 GHz CPU frequency 

► High performance classic Floating Point Unit (FPU) for 

industrial applications 

• Supports IEEE Std. 754 FPU Double Precision 

Floating Point 

► Hybrid 32-bit mode to support legacy software and 

transition to 64-bit architecture 

• Register settings allow users to utilize 32-bit mode or 64- 

bit mode, easing transition to 64-bit architecture 




e5500: QorIQ 64-bit Core 

Introducing the 

e5500 core 

►Based on the e500 

Architecture with 64-bit 

ISA 

►Core frequency up to 2.5 

GHz 

►Up to 64 GB 

addressable memory 

space 

►Supports up to 512KB 

backside L2 cache 

►High performance 

classic FPU 

TM

Core Performance Comparison The new e5500 core 

1 

0.8 

0.6 

0.4 

0.2 

0 

Performance/Silicon Area Comparison 

1 

0.8 

0.6 

0.4 

0.2 

0 

e5500 Previous Power 

Architecture Generation 

e5500 Previous Power 

Architecture Generation 




► 2x more single core performance 

than previous Power Architecture 

generation 

► 2x more performance per silicon 

area than previous Power 

Architecture generation 

► Ideal for control plane applications 

that need the highest single core 

performance within an embedded 

power envelope 

TM


Architectures 




►Enablement 

►Q&A 




Agenda 

TM

QorIQ P5 

NEW: P5020, P5010 NEW! 

Up to 2.2GHz,

CPU 

CPU 

PowerQUICC/QorIQ P1, P2 

Freescale‟s Multicore System Architecture 




QorIQ P3, P4, P5 

Embedded Challenge Bus Architecture Fabric Arch Comments 

Core performance 

System Performance 

Power Architecture e500 

and e600 cores 

Classic interrupt shared 

BUS architecture 

Power Architecture e500 core 

w Front and backside cache 

Point to point Cross-bar 

Fabric 

Embedded Power Budgets

►Multicore interconnects must address: 

• Scalability of CPU cores, memory and I/O bandwidth 

• Flexible inter-processor communication programming models 

• QoS differentiation for control/data plane and network traffic 




Platform Interconnect is Critical to 

Delivering Multicore Scalability 

• Efficient memory subsystem including caching and hardware coherency 

►The CoreNet interconnect fabric on the QorIQ P4080 processor 

addresses the scalability needs of multicore processors 

P4080 

Aggregated interface bandwidth (MB/s) 

Read Bandwidth 

1 core 2 cores 8 cores 

TM

► 8 x e500mc Superscalar Cores 

► Tri-level cache hierarchy 

CoreNet on-chip fabric 

• Eliminates shared bus contention 

and supports dramatically higher 

address issue bandwidth to „feed‟ 

multiple cores 

► Hardware virtualization 

support 

► On-demand application 

acceleration – DPAA 

Data Path Acceleration 

Architecture 

► Industry-leading performance, 

process 

► Advanced 45nm process 

technology 

Multicore Communications Processors: QorIQ P4080 

Application-driven, balanced multicore architecture 

High-performance cores, coupled with on-demand application acceleration, 

on-chip fabric interconnect and high-speed interconnects. 




TM

►One of the challenges with 

multicore is how to efficiently 

utilize all the cores 

►Consolidation of software running 

on multichip onto a single 

multicore device has inherit 

difficulties: 

• Each software base believes it owns the 

full set of hardware resources 

• Some resources (memory, interrupt 

controllers, etc) will end up being shared 

• Consolidated software has to be modified 

to cooperate for shared hardware 

resources 

• Cooperation opens up the opportunity for 

bugs in one software system to impact 

another 




Virtualization Challenges & 4080 Solution 

►P4080 Supports true hardware 

partitioning and virtualization: 

• Each of the software systems and its 

associated private hardware resources are 

protected from other 

• Hardware that is shared is managed so that 

all software systems can use it without each 

system having knowledge of the others 

►Hardware support enables new 

use models: 

• With true isolation 3 rd party or customer 

software can run on the system without 

concerns of it impacting the rest of the 

system 

• Under utilized cores can be used to run 

more than one operating system 

• DRM and other secure data can be isolated 

and protected in its own partition 

TM




Datapath Acceleration 

Provides the infrastructure to pass packets to/from cores, 

hardware accelerators, and network interfaces. 

Adding cores without upgrading the infrastructure just 

moves the bottleneck elsewhere. 

► Parallel processing of packets: 

• Packets must be load spread across the cores in a meaningful manner 

• Packet ordering issues must be addressed 

► Shared network I/F and accelerators by multiple cores: 

• Traditional BD rings/lists (1 ring per MAC per QoS level per core) do not scale well as 

the number of cores and the number of network interfaces increase 

• Traditional buffer management techniques (e.g. software-replenished BD rings) do not 

scale well as data rates and the number of network interfaces increase 

► Separation of data buffering from data presentation 

► Inter-core communication and pipelining of work 

► Congestion management and avoidance with higher data rates and 

distributed processing. 

TM

Improved Application Efficiency From QorIQ Hardware 

HW Feature Benefits 

Packet Distribution Utilize all cores Equally 

Packet fields Extraction Saves cycles in cores 

Statistics Accelerator No atomic updates for statistics 

Hardware Queues Avoid software queues (especially when 

pipelining is involved) 

Hardware Buffer Pools Avoid core specific memory pools 




TM




QorIQ P2 Platform: P2020 

►Dual e500 Power Architecture ® cores 

• 800 - 1200 MHz 

• 512 KB Frontside L2 cache w/ECC, HW cache coherent 

• 36 bit physical addressing, DP-FPU 

►System Unit 

• 64/32-bit DDR2/DDR3 with ECC to 800 MHz data rate 

• Integrated SEC 3.1 Security Engine 

• Open-PIC Interrupt controller, Perf Mon, 2x I 2 C, Timers, 16 

GPIO’s, DUART 

• 16-bit Enhanced Local Bus supports booting from NAND 

Fash memory 

• One USB 2.0 Host controller with ULPI interface 

• SPI controller supporting booting from SPI serial Flash 

• SD/MMC card controller supporting booting from Flash 

cards 

• Three 10/100/1000 Ethernet controllers (eTSEC) w/ 

Jumbo Frame support, SGMII interface 

• Enhanced features: Parser/Filer, QOS, IP-Checksum 

Offload, Lossless Flow Control 

• IEEE ® 1588v2 support 

• Two Serial Rapid IO ® controllers with integrated message 

unit operating up to 3.125G Hz 

• Three PCI Express ® 1.0a controllers operating at 2.5 GHz 

►Process & Package 

• 45nm SOI, 1.05V +/- 50mV, 0C to 125C Tj 

• with -40C to 125C Tj option 

• 689-pin TePBGAII, 31x31mm 

TM




QorIQ P1 Platform – P1020 

►Dual e500 Power Architecture ® cores 

• 533 – 800 MHz 

• 256KB Frontside L2 cache w/ECC, HW cache coherent 



• 32-bit DDR2/DDR3 with ECC to 800 MHz datarate 


• Open-PIC Interrupt Controller, Perf Mon, 2x I 2 C, Timers, 

16 GPIO’s, DUART 

• 16-bit Enhanced Local Bus supports booting from 

NAND Flash 

• Two USB 2.0 controllers Host/Device support 



cards 

• TDM interface 



• Enhanced features: Parser/Filer, QOS, IP- 

Checksum Offload, Lossless Flow Control 

• IEEE ® 1588v2 Support 

• Two PCI Express ® 1.0a controllers operating at 2.5 GHz 

• Power Management 


• 45nm SOI, XX +/- XX, 0C to 125C Tj 

• with -40C to 125C Tj option 

• 689-pin TePBGAII, 31x31mm, 1.0mm pitch 

TM

Security 

Accel 

XOR 

QUICC 

Engine 

UTOPIA, 

TDM, MII 

32KB 

I- 

Cache 

e500 

Core 

3x 

GE 

MAC 

32KB 

D- 

Cache 

256KB 

L2 

Coherency Module 

System System Bus Bus 

DMA 

32KB 

I- 

Cache 

e500 

Core 

32KB 

D- 

Cache 

On-Chip Network 

PCI 

Express 

x4 SerDes 

PCI 

Express 




QorIQ P1 First Derivative – P1021 

DDR2/DDR3, 

SDRAM 

Controller 

Enhanced 

Local Bus 

Perf Mon, 

DUART, MPIC 

2x I2C, Timers 

USB2.0 

SD/MMC 

SPI 

32b 

16b 

►Dual e500 cores; 533 - 800 MHz 

• 256KB Frontside L2 cache w/ECC, HW cache coherent 



• 32-bit DDR2/DDR3, 800 MHz data rate w/ECC 


• Open-PIC Interrupt Controller, Perf Mon, 2x I 2 C, 

Timers, 16 GPIO’s, DUART 

• 16-bit Enhanced Local Bus supports booting from 

NAND Flash 

• USB 2.0 controllers Host/Device support 



cards 



• IEEE ® 1588v2 Support 

• QUICC Engine for protocol off load and legacy 

interfaces 

• TDM interfaces with HDLC support 

• UTOPIA-L2 interface for ATM support 

• Two PCI Express ® 1.0a controllers operating up to 

2.5Gbps 

• Power Management 


• 45nm SOI, 0.95V+/-50mV, -40C to 125C Tj 

• 689-pin TePBGAII 

TM

eOpenPIC 

PreBoot Loader 

Security Monitor 

Internal BootROM 

Power Mgmt 

SD/MMC 

SPI 

DUART 

4x I2C 

2x USB 2.0 PHY 

Clocks/Reset 

GPIO 

CCSR 

eLBC 

Pattern 

Match 

Engine 

2 

What‟s New? QorIQ P5 Series P5020 Block Diagram 

Power Architecture ® 

512 KB 

Backside 

e5500 Core 

L2 Cache 32 KB 32 KB 

D-Cache I-Cache 

Frame Manager 

Parse, Classify, 

Distribute 

10GE 

Buffer 

CoreNet 

Coherency Fabric 

Peripheral 

PAMU PAMU 

PAMU PAMU 

Access Mgmt Unit 

SEC 

4 

RAID 

5/6 

Engine 

Queue 

Mgr. 

Buffer 

Mgr. 

SRIO 

Mgr. 

1GE 

1GE 




1GE 

1GE 

1GE 

PCIe 

PCIe 

SRIO 

1024 KB 

Frontside 

L3 Cache 

DMA 

x2 

18-Lane 5 GHz SerDes 

SRIO 

PCIe 

PCIe 

SATA 2.0 

64-bit 

DDR-3 

Memory Controller 

SATA 2.0 

PAMU 

Real Time 

Debug 

Watchpoint 

Cross 

Trigger 

Perf CoreNet 

Monitor Trace 

Aurora 

►2x e5500 Power Architecture ® 

• 2x 64-bit cores (up to 2.2 GHz) with 512 KB 

backside L2 cache 

• Dual 1MB Shared L3 Cache w/ECC 

►Memory Controller 

• Dual 32/64bit DDR3/3L w/ECC up to 1.3 

GHz 

►Ethernet 

• 5 x 10/100/1000 Ethernet controllers 

• 1 x 10GE controller (XAUI) 

►High Speed Interconnect 

• 4 PCI Express ® (PCIe) 2.0 controllers 

• 2 Serial RapidIO ® (SRIO) 1.3 + 2.0 

controllers 

• 2 SATA 3Gb/s 

• 2 USB 2.0 with PHY 

►CoreNet Switch Fabric 

►Trusted Architecture 

►Data Path Acceleration Architecture 

• Security Engine (SEC) 

• Pattern Matching Engine (PME) 

• RAID 5/6 Engine 

• Enhanced RapidIO Messaging (Rman) 

►Device 

• 45nm SOI Process 

• 1295-pin package: Pin compatible with P4080 

and P3041 

TM

eOpenPIC 




Power Mgmt 

SD/MMC 

SPI 

2x DUART 

4x I2C 


Clocks/Reset 

GPIO 

CCSR 

eLBC 

32b 

Rapid 

IO 

RMan 

Pattern 

Match 

Engine 

2.0 

What‟s New? QorIQ P3 Series P3041 Block Diagram 


128 KB 

Backside 

e500mc Core 

L2 Cache 32 KB 32 KB 


CoreNet 


1024 KB 

Frontside 

L3 Cache 

64-bit 

DDR3/3L 


Peripheral 

PAMU PAMU 

PAMU PAMU PAMU 


SEC 

4.0 

Queue 

Mgr. 

Buffer 

Mgr. 

Frame Manager 


Distribute 

10GE 

Buffer 

1GE 

1GE 




1GE 

1GE 

1GE 

PCIe 

PCIe 

SRIO 

SRIO 

DMA 

x2 


PCIe 

PCIe 

SATA 2.0 

SATA 2.0 

Real Time 

Debug 

Watchpoint 

Cross 

Trigger 

Perf CoreNet 

Monitor Trace 

Aurora 

►Quad e500mc Power Architecture ® 

• 4 cores (up to 1.5 GHz) with 128KB backside 

L2 cache 

• 1 MB Shared L3 Cache w/ECC 


• 32/64bit DDR3/3L w/ECC up to 1.3 GHz 

►Ethernet 

• 5 x 10/100/1000 Ethernet controllers 

• 1 x 10GE Controllers 


• 4 PCI Express ® (PCIe) 2.0 controllers 

• 2 Serial RapidIO ® (SRIO) 1.3 + 2.0 

controllers 

• 2 SATA 2.0 

• 2 USB 2.0 w/PHY 


►Trusted Architecture 

►Data Path Acceleration Architecture 

• Security Engine (SEC) 

• Pattern Matching Engine (PME) 

• Enhanced RapidIO Messaging (Rman) 

►Device 


• 1295-pin package, pin compatible with P4040 

37.5x37.5mm 

TM

eOpenPIC 




Power Mgmt 

SD/MMC 

SPI 

2x DUART 

4x I2C 


Clocks/Reset 

GPIO 

CCSR 

eLBC 

16b 

Rapid 

IO 

RMan 

Pattern 

Match 

Engine 

2.0 

Power Architecture 

e500mc Core 

32 KB 32 KB 





QorIQ P2 Series P2040 Block Diagram 

CoreNet 


1024 KB 

Frontside 

CPCache 

64-bit 

DDR3/3L 


Peripheral 

PAMU PAMU 

PAMU PAMU PAMU 


SEC 

4.0 

Queue 

Mgr. 

Buffer 

Mgr. 

Frame Manager 


Distribute 

1GE 

1GE 

Buffer 

1GE 

1GE 

1GE 

PCIe 

SRIO 

SRIO 

PCIe 

DMA 

x2 


PCIe 

SATA 2.0 

SATA 2.0 

Real Time 

Debug 

Watchpoint 

Cross 

Trigger 

Perf CoreNet 

Monitor Trace 

Aurora 

►Quad e500mc Power Architecture® 

• 4 cores (up to 1.2GHz) 

• 1MB Shared CoreNet Platform Cache w/ECC 


• DDR3/3L SDRAM up to 1200MHz 

• 32/64 bit data bus w/ECC 


• 3 PCIe 2.0 Controllers 

• 2 sRapidIO 2.1 Controllers 

Type 9 and 11 messaging 

• 2 SATA 2.0 


►Ethernet 

• 5 x 10/100/1000 Ethernet Controllers 

Or 4x 2.5Gb/s SGMII 

• All w/ Classification, H/W Queueing, policing, 

and Buffer Management, Checksum Offload, 

QoS, Lossless Flow Control, IEEE 1588 

• Up to 5 SGMII or 2.5Gb/s SGMII, 2 RGMII 

►Datapath Acceleration 

• SEC 4.0 

• PME 2.0 

►Device 


• 783-pin package 

23x23mm, 0.8mm pitch 

• 10W thermal max (est) w/o I/O at 1.0GHz 

TM

Protection Against 

Freescale QorIQ Platform‟s - Trust Architecture 

► Theft of Functionality - loss of control of the system’s functionality 

► Theft of Data - where a data protection policy exists, loss of data to an unauthorized party 

► Theft of Uniqueness - loss of product differentiation through reverse engineering, 

duplication, and unapproved inter-operability. 

Relying on 

► Secure Boot – start from Trusted code base or don’t start at all 

► Strong Partitioning of the System – isolation of cores from each other to provide 

redundancy and data corruption protection between critical functions 

► Threat detection – internal and external security event detection 

► Secure Debug 




TM

►Secure Platform Boot: 

Configured to boot from 

on-chip ROM 

• CPU#0 begins to boot from on-chip 

ROM, all other CPUs held in reset 

• CPU executing from on-chip trusted 

boot code (provided by FSL) 

performs initial SoC configuration 

and health checks, verifies a 

signature over the Hypervisor 

micro-kernel, stored in the NV 

RAM of OEM’s choice 

►Secure boot insures that the system 

begins executing trusted code. This 

trusted code can test the 

trustworthiness of other system code 

before allowing it to execute. 

Note: ‘Trusted’ = passes signature 

check. Don’t sign it if you don’t trust it! 

P4080 




Trusted Boot and Hypervisor 

External 

Tamper 

Detect 

TM


Architectures 




►Enablement 

►Q&A 




Agenda 

TM

Freescale 

Curtiss Wright 

KONTRON 

Emerson Network 

Power 

EuroTech 

GE Intelligent 

Platforms 

Interphase 

Mercury 

RadiSys 

TQ Embedded 

Power Architecture ® Technology‟s Growing Market Reach 

- Single Board Computer Partners 

Subset of a comprehensive partner ecosystem 

COM Express ATCA Blades AMC Compact PCI PMC’s 

ATCA AMC 

COM 

Express 

Compact- 

PCI 




 

VME PMC’s ATX,uATX 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TM

What‟s New? - Easing the “Make vs Buy” Decision 

► Freescale Development Systems 

with production-ready COM Express 

platform 

• QorIQ products P4080, P2020, P1022 

• Linux ® BSP from Mentor Graphics 

• CodeWarrior 90 day license 

► Availability - $1499/System 

• P2020COME-DS-PB November, 2010 

• P4080COME-DS-PB December, 2010 

• P1022COME-DS-PB January, 2010 

• 




► Emerson Network Power production 

ready COM Express boards 

• COMX-P2020 

P4080 

• COMX-P4080 

95 x 125 mm 

P2020 

95 x 95 mm 

P1022 

95 x 95 mm 

P2020 – dual core @ 1.2 GHz/core 

X4 USB, PCI Express ® and 3 GigE ports 

2 GB of DDR3 – 800 MHz (not Included) 

2-3D Graphics Processor Unit 

P4080 – 8 cores @1.5 GHz/core 

X8 USB, 3 GigE and PCI Express ports 

Local Bus 

Dual banks of 2 GB of DDR# - 1333 MHz (not 

included) 

• COMX-P1022 

P1022 – Dual core @ 1.067 GHz/core 

– w/Integrated Digital Display Output 

X4 USB, x2 PCI Express, dual GigE ports 

X2 SATA 

2 GB DDR3-800 MHz 

TM

In the News: Application-Specific Focused Reference Designs: P2020-UTM 

Production-ready BOM & performance-optimized, fully integrated solutions 

NETWORKING OEM 

VortiQa Software 

HARDWARE ODM/CM 

END USER PRODUCT 

(OEM Branding + Channel + Support) 

PRODUCTION READY SECURITY SOFTWARE 

APPLICATION 

(Software Platform + Integration with Freescale Silicon 

+ Integration testing + Regression testing 

+ Certifications, where applicable) 

QorIQ or MPC silicon based H/W Platform 

(PCBA + OS and Board support package) 




► Announced at RSA Show – March 2010 

► QorIQ Silicon: P4080, P2020, P2010, P1020 

► (+) VortiQa Software for Enterprise Equipment 

► (+) Ecosystem Partners 

► SOLUTION OUTCOME: 

• Cost optimized: UTM appliance portfolio, from lowend 

to high-end, from major ODMs (2-4Gbps to 20 

Gbps) 

• Ready to ship: FCC, UL and CE certified 

• Performance: Performance optimized software 

TM

In the News: Application Specific Focused Reference Designs 

May 31, 2010 – Freescale Semiconductor, a leader in embedded processors for 

communications, consumer access and intelligent industrial and aerospace applications, 

and Atheros Communications, a leading developer of wired and wireless 

communication semiconductors, have collaborated on a production-ready reference 

design for high-performance and cost-effective WiFi access points for enterprise offices 

and small-to-medium sized businesses (SMB). 

The solution leverages the industry leading performance of Freescale’s QorIQ P1020 

system-on-chip (SoC) and Atheros’ 3-stream XSPAN ® chipset with Signal-Sustain 

Technology (SST3) to accelerate time to market for 802.11n access points capable of 

servicing corporate network environments. Dual-band, dual-concurrent products based 

on this combination can deliver up to 600Mbps of actual throughput and greater 

wireless coverage to support a wide range of demanding enterprise and SMB 

applications that boost productivity and increase employee mobility… 

Application challenges 

► Highly competitive market –time to market and revenue 

► Power over Ethernet (IEEE®802.3af) 

► In-door and out-door applications 

► Ability to stream data wirelessly with little interruption 

► Ability to secure data streams using high levels of encryption 

Device advantages 

► Time to market, class B certified production ready system 

► Support for Power over Ethernet and 802.11n with best in class application throughput 

► Support for miniPCI-Express, and extended temperature 

► Variable applications depending on configuration 




TM

In the News: Freescale Announced Strategic Alliance 

► Freescale has signed new strategic partnerships with Enea, Green 

Hills and Mentor Graphics for Freescale’s QorIQ, PowerQUICC and 

StarCore portfolios 

► These deep partnerships call for unprecedented levels of collaboration 

across the entire silicon lifecycle 

• IP sharing 

• Joint investments in technology and product roadmaps 

• Go-to-market partnership 

► Establishes extremely comprehensive enablement support for QorIQ, 

PowerQUICC and StarCore devices 

► Plans call for adding more strategic partners over time 




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e5500 Ecosystem Overview 

Ecosystem Partner Solution Offering for e5500 

Real Time Operating System support 

Complete portfolio of software & hardware 

development tools, trace tools and real-time operating 

systems 

Commercial grade Linux ® OS solution 

Tool chain support for new core technology 

Provides Simics model of core technology to enable 

early 64-bit development. 

Power.Org supports the Power Architecture ® core 

technology using the new ISA v2.06 

TM

Platform Requirement: Mixed Control/Data Plane 

► Data plane/signal processing cores act as programmable accelerators for network 

processing managed on control plane. Other cores provide special services 

(e.g. virus scan) 

► Broad OS support providing SMP/AMP support 

► Broad spectrum from OS vendors who actively support multiple market segments 

Control Plane Data/Signal Processing Other Services 

L2 Cache 


Core 


SMP O/S 

L2 Cache 


Core 


L2 Cache 


Core 


AMP O/S 

(shared code) 

L2 Cache 


Core 


CoreNet Coherency Fabric 

L2 Cache 


Core 





L2 Cache 


Core 


AMP 

O/S 

L2 Cache 


Core 


L2 Cache 


Core 


Front-side 

L3 Cache 

AMP 

O/S 

DDR2/3 

Memory 

Controller 

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World Class Alliances 

Strategic Technology Collaboration 

e200 e300 e500 e600 

SOC integrated devices 

Embedded power budgets 

Networking life cycles 

TM 

Networking/security IP 

Content Aware Packet Processing 

The Ecosystem to Enable the Connected World 

Architecture 

Alliance 

Applications 

Secure 

Networks 

Optimize application-specific stacks for continual 

improvement in network security solutions 

Power 

Architecture ® 

Technology 

Hardware 

Hardware 

Partners 

Tools/OS 

Software 

Partners 




Development and production systems 

in standard industry form factors 

Value Partners: Enable faster time to market 

and longer time in market 

TM 

TM

MC68302 

68K core 

AIM Alliance 

Started 1991 

First silicon 1992 

QUICC MC68360 

68K core 

20 Years of Communications Processing Evolution 

PowerPC 603e 

First PowerQUICC 

communications processors 

Includes Communications 

Processor Module (CPM) 

PowerQUICC II 

603e Power core 

PowerQUICC III 

e500 Power core 


Host Processors 

MPC7xxx 

e600 core 

Security integration 

with PowerQUICC line 




Dual-core processor 

MPC8641D with e600 

Power cores 

PowerQUICC II Pro 


QUICC Engine 

Next-gen CPM / 

dual RISC engines 

Dual-core with 

integrated 

content 

processing 

MPC8572E with 


1989 1994 1995 1996 1997 1998 

2002 2003 2004 2005 2006 2007 2008 

In Production 

PowerPC 

75X 

GPON processor 

Integrated 

DSP + Power core 

TM

Freescale‟s Product Longevity Program 

► Freescale has a longstanding track record of providing 

long-term production support for our products 

► Freescale is pleased to provide a formal product 

longevity program for the market segments we serve 

• For all market segments in which Freescale participates, 

Freescale will make a broad range of devices available for 

a minimum of 10 years 

• Life cycles begin at the time of launch 

► A list of participating Freescale products is available at: 

www.freescale.com/productlongevity 




TM

►Thank you for attending this presentation. 

►We’ll begin the question and answer session. 




Q & A 

TM

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