S08 Core

►Family Overview
►Targets automotive multiplexing and high-end body
applications
►Pin compatible with existing S12 D-Family
►Enables higher system integrity at the ECU level
(MPU, ECC Supervisor Mode)
►Low current consumption, EMC, Code size density
►TIM Timer Modules (TIM subset of ECT,
downwards compatible)
►Memory Protection Unit
►Emulated EEPROM on board
►XGATE Co-processor provides additional
processing power to remove application
bottlenecks
•
Off-loads the CPU by providing high speed data transfer
(and data processing) between any peripheral module,
RAM and I/O ports. This is particularly useful in applications
such as automotive gateways where there are multiple
busses carrying heavy data traffic.
Family Differences
8 LIN/SCI
S12XE –
External Bus Interface
In Production
TM
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21
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3 SPI
2 IIC
GPIO
FMPLL
XGATE
64KB RAM
1MB Flash
4KB EEPROM
MPU CRG
DBG INT
S12XCPU
50MHz Bus
Note: block diagram represents the S12XEP100
Device Flash RAM CAN SCI IIC ADC Timer PIT I/O
S12XEP100 1 MB 64 KB 5 8 2 2x16-Ch., 12-bit 8-Ch., 16 -bit 8-Ch 152
S12XEP768 768 KB 48 KB 5 8 2 2x16-Ch., 12-bit 8-Ch., 16 -bit 8-Ch 152
S12XQ512 512 KB 32 KB 4 6 2 2x12-Ch., 12-bit 8-Ch 11
S12XQ384 384 KB 24 KB 4 4 1 2x12-Ch., 12-bit 4-Ch 11
S12XET256 256 KB 16 KB 3 4 1 2x12-Ch., 12-bit 4-Ch 11
5 MSCAN
ATD 12b 32ch
Timer 16b 8ch
ECT 16b 8ch
8ch Periodic
Interrupt Timer
PWM 8b 8ch
80/112/144 LQFP,
208 MAPBGA