8086 Microprocessor (cont..) - nptel

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V CC 8086 GND A 0 - A15, A 16 / S 3 –A 19 /S 6 INTR _____ INTA ______ TEST INTERRUPT INTERFACE ADDRESS / DATA BUS D 0 - D 15 NMI RESET MPU ALE ___ BHE / S 7 __ HOLD HLDA V CC ____ MN / MX DMA INTERFACE MODE SELECT MEMORY I / O CONTROLS M / IO ____ RD _____ WR _____ DEN READY __ DT / R CLK M. Krishna Kumar MM/M1/LU3/V1/2004 6
Internal Architecture of 8086 • 8086 has two blocks BIU and EU. • The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. • The instruction bytes are transferred to the instruction queue. • EU executes instructions from the instruction system byte queue. M. Krishna Kumar MM/M1/LU3/V1/2004 7
Page 1 and 2: 8086 Microprocessor (cont..) • It
Page 3 and 4: 8086 Microprocessor (cont..) Minimu
Page 5: Pin Diagram of 8086 GND AD 14 AD 13
Page 9 and 10: Internal Architecture of 8086 (cont
Page 19 and 20: Minimum Mode Interface ( cont..)
Page 31 and 32: Maximum Mode Interface • When the
Page 33 and 34: CLK INTR Vcc GND LOCK CLK CRQLCK RE
Page 35 and 36: Maximum Mode Interface (cont..) Sta
Page 37 and 38: Maximum Mode Interface (cont..) •
Page 43 and 44: Minimum Mode 8086 System (cont..)
Page 49 and 50: Minimum Mode 8086 System (cont..) M
Page 51 and 52: Minimum Mode 8086 System (cont..) T
Page 53 and 54: Minimum Mode 8086 System (cont..) C
Page 55 and 56: Maximum Mode 8086 System (cont..)
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Maximum Mode 8086 System ( cont..)
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Internal Registers of 8086 (cont..)
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Internal Registers of 8086 • Auxi
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Addressing Modes • Indexed :- 8-b
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Memory (cont..) • 32-bit addresse
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Memory (cont..) • Accessing data
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Interrupts (cont..) The processor h
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Interrupts • Single-step interrup
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8086 Microprocessor (cont..) - nptel

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