Lec14

Lecture 14:
Programmable Logic Devices
Objectives:
• Identify programmable logic devices and understand their usage.
• Understand the structure and size of the ROM, PLA and PAL
• Implement Boolean functions using ROM’s, PLAs and PALs
• Recognize the array logic graphic symbol and appreciate its usage in large
programmable logic devices
Introduction
Integrated circuit categories are: SSI, MSI, LSI, and VLSI. MSI devices have a
complexity of approximately 10 to 1000 ICs in a single package. Several
combinational circuits are available in MSI form, e.g. adders, subtractors, decoders,
encoders, multiplexers,… etc.
Programmable Logic Devices are IC's with internal logic gates (arrays of AND gates
and OR gates) connected through fuses to establish a pattern of connections. A
typical PLD may have hundreds to millions of gates interconnected thru hundreds to
thousands of internal paths.
Three types of PLD's are studied here:
a. Programmable Read Only Memory (PROM)
b. Programmable Logic Array (PLA)
c. Programmable Array Logic
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Memory
A memory unit is a device to which binary information is transferred for storage and
from which information is retrieved when needed for processing.
(a) RAM → random -access memory with both read & write operations.
Examples are: Static RAM (SRAM), Dynamic RAM (DRAM).
(b) ROM → read-only memory with read operation only. Examples are:
PROM, EPROM, EEPROM.
A memory stores information in groups of bits called words. A memory word is a
group of 1s and 0s. A group of 8 bits is called a byte. Most computer memories use
words that are multiple of byte. The capacity (size) of memory is usually stated as
total number of bytes that the unit can store.
2 10 =1K, 2 20 =1M, 1G=2 30 ……..2 16 =...K; 2 21 =...M; 2 32 =….G.
“the number of address lines k is independent of the number of bits in each word”.
Read Only Memory (ROM)
A ROM is considered a programmable device where binary information can be stored
and kept even when power supply is switched off. A ROM consists of a decoder and
array of fused (programmed) OR gates. This is shown in the following Figure.
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The required paths in ROM may be programmed in different ways: 1-mask
programming ROM; 2-PROM; 3-EPROM (ultraviolet light); EEPROM (like flash
memory)
Fig. Internal logic of a 32 X 8 ROM
The ROM truth table shows the pattern of the fuses as programmed inside the ROM.
The following truth table is an example for the 32 X 8 ROM.
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A cross indicates a connection (1), and no cross indicates (0) as shown in the
following diagram.
Example
Design a combinational circuit using ROM that accepts a three bit number and
generates an output equal to the square of the input number.
All what we do is to generate a truth table for the required circuit. Most times this is
all what is needed. On some occasions, we may be able to reduce the number of
outputs required from the ROM.
For this circuit we require six outputs, because the largest output is the binary
equivalent of 7 2 = 49 →110001 2
The Truth Table
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Fig. PLA with three inputs, four product terms, and two outputs
Combinational Circuit Implementation with PLA
When implementing combinational circuit using PLA, we must reduce the number of
product terms. Number of literals in each product term is not important because all
variables and their complements are available.
In order to reduce the number of product terms, we have to simplify the functions
and their complements in order to find the combination that result in the minimum
number of product terms.
The size of the PLA is determined by the number of inputs, number of product terms
and the number of outputs (Ex. 16x48x8).
Example
Implement the following two Boolean functions using a PLA.
First, we simplify the functions and their complements
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and
and
( F, F ), ( F′ , F ), ( F, F′ ), ( F′ , F′
)
Considering the four possible pairs 1 2 1 2 1 2 1 2
The minimum number of product terms is (4) and is obtained if we implement F 1 in
complement form and F2 in true form. The following PLA programming table is used.
Programmable Array Logic (PAL)
PAL has a fixed array of OR gates and programmable array of AND gates. It is easier
to program than the PLA but is less flexible. It is suitable to implement a number of
Boolean functions which have no or a few overlapping product terms.
When we implement Boolean functions with PAL, we must simplify the functions to
fit the sections of the PAL. A product term cannot be shared among two or more OR
gates. If the function cannot fit in one section, then we may use two sections to
implement the function.
A typical PAL integrated circuit may have 8 inputs, 8 outputs, and 8 sections, each
consisting of an 8-wide AND-OR array. The output terminals are sometimes driven by
three-state buffers or inverters.
The logic diagram of a typical PAL is shown in the following Figure.
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3 programmable
AND gates in each
section and 1 OR
gate
Fig: PAL with 4 inputs, 4 outputs, and a 3-wide AND-OR structure.
Example
Implement the following Boolean functions using a PAL that has four sections with
three product terms each.
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Simplifying the functions results in the following functions:
The PAL programming table is given below:
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FPGA
Field-programmable gate array (FPGA) is a complex PAL that is configured by
downloading a stream of bits into the device to configure transmission gates to
establish the internal connectivity required by specified logic function (combinational
or sequential).
FPGA is a VLSI circuit that can be programmed at the user’s location. A typical FPGA
consists of an array of hundreds or thousands of configurable logic blocks (CLBs)
surrounded by programmable input and output block (IOB).
A typical CLB consists of look-up tables (LUT), multiplexers, gates and flip-flops.
Figure below shows a portion of the structure of an FPGA.
CLB
Logic module
CLB
Logic module
Local
interconnect
Logic module
Logic module
Local
interconnect
Logic module
Logic module
Logic module
Logic module
Global column
interconnect
Global row
interconnect
Conclusion
The design with PLD, CPLD or FPGA requires extensive computer-aided design (CAD)
tools to facilitate the synthesis procedure. Among the tools that are available are
schematic entry packages and HDLs such as ABEL, VHDL and Verilog.
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