ANNUAL REPORT 2012

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Extended Abstracts JUMP - Jump to Manycore Platforms JUMP - The JUmp to Manycore Platforms Anders Åhlander (SAAB), Bertil Svensson (HH), Hoai Hoang Bengtsson (HH/SAAB), Per Ericsson (SAAB), Per-Arne Wiberg (F2M), Suleyman Sava (F2M), and Zain-ul-Abdin (HH) 1 Challenges Development of advanced embedded signal processing systems, such as smart phones, multimedia devices, radio base stations, and radar systems require high performing parallel computer platform solutions. Although the specific design and implementation requirements of the different kinds of applications within this domain are not the same, they share many functional characteristics and typically require performance-, cost- and engineering efficient development solutions in order to be competitive on the commercial market. The consensus today is that increased parallelism in various forms is the main way ahead for providing significant performance improvement in advanced computing systems while keeping the energy consumption and heat dissipation under control [1]. Manycore processor architectures offer scalable parallelism and the performance needed for implementation of the functionality required in high-end embedded sensor- and communication systems. However, the increasing programming complexity of such highly parallel computing technology will to a large degree affect existing product development and in particular software development processes. Industry need to take a jump in terms of re-targeting from existing software development solutions to solutions compatible with evolving manycore platforms, i.e., not just one parallel platform but a sequence of ever more parallel architectures. The main challenge ahead for industry is how to efficiently perform the technology shift from current application hardware platforms to future generations of platforms including heterogeneous manycore technology. The scientific challenge is to reconcile two conflicting needs: development productivity and performance efficiency. Software portability, program correctness and programmer productivity all demand that programs are written in a high-level language capable of expressing application-level parallelism while abstracting away platform dependent physical parallelism. In contrast, performance efficiency is traditionally better achieved by developing code tuned for the specific target hardware. Software development tools need to bridge this gap. 2 Goals The overall goal of the project is to investigate and develop programming and development technologies enabling the efficient design and programming of highly integrated embedded manycore systems. This will in particular deal with embedded signal processing systems where traditional generic processor architectures and their corresponding programming models are not efficient enough to meet the required performances and/or other non-functional system properties. The project will focus on studying new performance- and energy-efficient manycore processors and developing new parallel programming tools with the aims to, • enable engineering-efficient development and power efficient implementations, • support platform independency and hardware/software scalability, and • present solutions that can evolve with future manycore architectures. A concrete objective in order to demonstrate the approach is to develop a convenient programming tool for the Adapteva manycore used in signal processing (radar signal processing and video encoding). 3 Engagement 3.1 Halmstad University (HH) HH will focus on (i) investigation of trends in processing architectures suitable for high-performance embedded signal processing and, in particular on (ii) investigation of programming and scheduling tools for scalable, platform independent signal processing software development on manycore hardware. Important parts of (ii) are intermediate languages and models of computation. 3.2 SAAB SAAB will focus on investigating future trends in application requirement and how the manycore capability meets the performance requirements of future signal processing systems. In particular, SAAB is interested in: • Scalable, heterogeneous, and reconfigurable parallel architectures for complex multi-function radar systems. • Software models, which are scalable and reusable for different parallel architectures. • How to minimize the impact on the application’s nonfunctional behaviour when changing hardware platform. 3.3 Free2move (F2M) F2M will focus on research questions related to energy efficiency. F2M’s core interest is handheld or wearable communication devices for sports and harsh environments. The latest generation manycore architectures have promising properties. The programming tool chain is however lagging behind. F2M’s particular interests are: • Low power signal processing for voice and video streaming • Exploration of the mapping of video codecs on the low power floating-point manycore architecture. 3.4 International Engagement • The project will have active involvement from Adapteva Inc., a privately held fabless semiconductor company based in Lexington, Massachusetts. Adapteva has developed maybe the world’s most energy efficient manycore microprocessor and is in the process of scaling this up to hundreds of processors. The company’s technology thus offers high performance at very low power, which is exactly what is asked for by the industrial partners in the project. Adapteva will supply the project with hardware, software development tools, and detailed knowledge of the 20 CERES Annual Report <strong>2012</strong>
characteristics of the architectures. The close contacts with the company will enable the researchers to get a more accurate view of the expected up-scaling and other development of manycore architectures. • The project will make use of the established connections with other partners from SMECY project such as Verimag/ UFJ (Universite Joseph Fourier) and open new connection with other potention partner in Europe: ETH Zurich. 4 Working Plan The complexity of future embedded manycore systems development requires an overall strategy establishing a close interaction between applications, programming models and hardware architecture platforms. The project is organized into three work packages: 4.1 WP1. Studies of challenges in future signal processing applications An important aspect when it comes to the applications is the trend, i.e., the way that the requirements increase over time. We must find application development solutions for manycore platforms that can manage a continuous increase of the signal processing requirements. The requirements come from increased raw performance demands and/or performance per watt demand, as well as increased functional complexity. The objective of this WP is to give the application requirements needed to study how/if many-cores can increase the processor performance and allow the implementation of new features requested by future DSP applications. Outcome of this WP can be used as input for WP2 and WP3. 4.2 WP2. Investigation of potential hardware architectures for future signal processing applications The key objective of this work package is to analyze the important trends in massively parallel processor architectures that could be used for future embedded signal processing applications. The investigations in this work package will focus on identifying the salient characteristics of the selected architectures: Adapteva, CoherentLogix and ElementCXI. Partners Halmstad University (HH) SAAB AB, business area electronic defence systems (SAAB) Free2move AB (F2M) Adapteva, Inc. (AI) Duration and Financial The project will run over 2 years (Sept 2011 – August 2013) Project size: ca 4.5 MSEK or more HH: 3.0 MSEK (=67%), funded by KKS (CERES+) SAAB EDS: 900 KSEK (=20%) in kind F2M: 600 KSEK (13%) in kind Adapteva: TBD (not counted as matching to KKS) References 1. K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams and K. A. Yelick, ”The Landscape of Parallel Computing Research: A View from Berkeley”, Technical Report No. UCB/EECS-2006-183, EECS Department , University of California, Berkeley, Dec 18, 2006 2. Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, and André DeHon, “Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine”, In Proceedings of the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002), Monterey CA, pp. 196- -205, Feb. 24--26, 2002. 3. J. Eker, J. Janneck, E. A. Lee, J. Liu, X. Liu, J. Ludvig, S. Sachs, Y. Xiong, “ Taming heterogeneity - the Ptolemy approach”, Proceedings of the IEEE, 91(1):127-144, January 2003. 4. P. Bourgos, A. Basu, S. Bensalem, K. Huang, J. Sifakis, Verimag Research Report N0 TR-2011-1, January 2011. 5. W. Haid, K. Huang, I. Bacivarov, and L. Thiele, Multiprocessor SoC Software Design Flows. IEEE Signal Processing Magazine, 26(6):64—71, Nov. 2009 4.3 WP3. Methods and Tools for Application Development on Manycores In this work package we will investigate tool infrastructure for DSP software development on manycore processors. We have chosen one tool chain from SMECY project: DOL/BIP [4], which was developed at ETH Zurich and Verimag. Inparticular we focus on using DOL (Distributed Operation Layer) [5] for modelling signal processing applications and architecture. The goal of the project is to complete development of the tool flow from software model to code generation for chosen architecture. One of the key components to an efficient implementation of such a tool flow is to make use of suitable and well-defined parallel models of computation, which capture parallelism and expose design time predictable execution behaviour. CERES Annual Report <strong>2012</strong> 21
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