ANNUAL REPORT 2012

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HIPEC - High Performance Embedded Computing HIGH-PERFORMANCE EMBEDDED COMPUTING V. Gaspes 1 , E. Gebrewahid 1 , T. Nordström1, Zain-ul-Abdin 1 1. Centre for Research on Embedded Systems, Halmstad University, SE-301 18 Halmstad, Sweden HiPEC is a project partly financed by SSF, the Swedish Foundation for Strategic Research, in which CERES collaborates with Lund University and Linköping University. The project started on July 2011 and addresses the development of programmable parallel platforms for high performance signal processing applications. Two research groups at Lund and Linköping universities address the development of parallel hardware architectures while CERES and a group at Lund University develop programming languages and tools for programming these and other commercial parallel architectures. 1. Background and Motivation Parallelism is the main way to provide significant performance improvement of embedded systems while keeping energy consumption low. Streaming applications are good candidates for parallelization since they are regular and exhibit data parallelism. Traditionally, ASICs have been designed to implement specific functionality with high performance and low power constraints. Recently, coarse-grained reconfigurable array architectures have been proposed as flexible but still high performance alternatives. It is therefore expected that a DSP computing system, increasingly parallel and reconfigurable, will be one of the dominating parts in OEM equipments in 2020 because it maximally exposes opportunities of parallelization. In this project, we address reconfigurable array processor architectures as well as software tools for their programming. A massively parallel execution platform with powerful computing nodes and hierarchical interconnection struc- ture suitable for streaming applications will be developed and studied. The distinct features of our software development approach are the use of the CAL language for programming of these architectures as well as the development and use of tools for timing and energy analysis at early design stages. Combining both hardware and software experts in the same project provides a strong basis for covering the whole spectrum of this new technology. 2. Problem Up until recently, the evolution of computing machines was characterized by an unabated increase in performance. This progress was in large part due to steady advances in silicon manufacturing technology, which provided cheaper, smaller, and faster circuits, and, to some degree due to improvements in processor architecture that exploited those advances to create ever faster processors. This development, however, has considerably slowed down in the last few years. As a result of these developments, the computational power of individual processors is no longer increasing, and consequently the only way to significantly improve the performance of a computing machine is to use more processors operating at the same time: the age of parallelism has finally arrived. The model of the sequential instruction set computer has been a very powerful abstraction that brought enormous benefit to the computing community. This is in stark contrast with the situation in the world of parallel machines, where no such nearly-universal machine model exists. There is no common machine model tying these platforms together, and consequently there are no common tools, no common languages, and no common code in the form of applications or libraries. In this project, we propose to narrow this gap and work on both massively parallel hardware platform architecture and tools for software development. 3. Approach We focus on stream/dataflow computing and related parallel computing platforms and programming models. In our view, only a synergy between the hardware platform and the software paradigm can truly bring forth the benefits of parallelism that computing strives after today. For this purpose we adopt an actor based programming paradigm realized in the programming language CAL and we design and study massively parallel, hyerarchical and heterogeneous architectures. The CERES team will focus on tools for mapping programs written in CAL and on studying forms of organizing the networks that lead to opportunities to reduce power consumption. Figure 1 exposes the vision for the design flow using the tools resulting from the project. Figure 1: Proposed design flow for mapping CAL applications onto reconfigurable platforms. 24 CERES Annual Report 2012
PARTNERS AND STATUS Project funding: SSF, Rambidrag Elektronik/Fotonik 2010, HiPEC: Högpresterande inbyggda system, diarienummer RE10-0081. The project started on July 2011. One of the young researchers left the university and moved to industry. One of the PhD students abandoned her studies due to her personal situation. One project addressing the use of similar methods but addressing commercial architectures has started as a collaboration between Lund and CERES. The project leader is Krzysztof Kuchcinski. Veronica Gaspes is coordinator for the CERES group. Results from the project will form part of the PhD theses of Essayas Gebrewahid (admitted at Halmstad University in the fall of 2011) and of a new PhD student that is being recruited during January 2013 to replace a PhD student that had to interrupt her studies. PUBLICATIONS [1] Zain-ul-Abdin, B. Svensson, “Occam-pi for programming of massively parallel reconfigurable architectures”, International Journal of Reconfigurable Computing, Vol. 2012, Article ID 504815, 2012. [2] Zain-ul-Abdin, E. Gebrewahid, B. Svensson, “Managing dynamic reconfiguration for fault-tolerance on a manycore architecture”, accepted for Reconfigurable Architectures Workshop, part of IEEE International Symposium on Circuits and Systems, May 2012. CERES Annual Report 2012 25
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