Curriculum vitae (pdf, en, 50 KB, 10/23/13)

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the requirements and constraints of the underlying CPU architecture. Current state of the art exploits formal specification of the device protocol, that are very difficult to extract when the hardware component is third party. Sara Vinco contributed by proposing a methodology that extracts the device communication protocol from the testbench of the device itself. Furthermore, the generated device driver can be customized with respect to the target architecture characteristics, by providing user specifications [JR.3], [IC.2], [IC.3], [IC.8], [IC.16]. The device driver generation methodology is also provided with a co-simulation platform, that connects the QEmu software emulator and SystemC to validate the generated code and hardware-software communication [IC.5]. HOMOGENEOUS FORMAL REPRESENTATION OF HETEROGENEOUS COMPONENTS Generating the necessary interfaces allows communication but preserves the degree of heterogeneity of the system. Co-simulation would allow to validate the system behavior, but it is unreliable as it implies to connect not only different simulators but also different models of computation and levels of abstraction. Furthermore, building a co-simulation framework for managing all the typical domains of embedded systems would be a very critical and time consuming operation. Exploiting top-down flows for designing the entire system is the complementary approach. Approaches such as Ptolemy and Metropolis allow to provide a system specification and to refine it through a number of steps, by choosing the appropriate model of computation and communication style of all components. On the other hand, top-down flows do not allow reuse of existing components. In this scenario, Sara Vinco proposed UNIVERCM, an automata based model of computation that covers all the typical domains of embedded systems. The starting heterogeneous components are automatically converted to the computational model, with transformations that preserve the starting behavior and that are implemented in automatic conversion tools, thus supporting a fully bottom-up flow [JR.1], [IC.9], [IC.13]. The homogeneous description is then used as a starting point for automatic generation of code for simulation and validation of the integrated system, or for efficient execution [IC.18],[IC.13]. HARDWARE TO SOFTWARE MIGRATION For long time, hardware implementation of a functionality has been considered more advisable than the corresponding software implementation for gaining better performance and efficiency. Indeed, hardware designs are customized to the needs and constraints of the surrounding system. A major drawback of this choice is the cost in terms of money and time: indeed, any change requires to go through a redesign process and to realize a new custom circuit, thus making integration and reuse extremely challenging. Furthermore, costs of silicon realization tend to be high for highly optimized and customized circuits. The development of highly and massively parallel processors, such as multiprocessors and GP-GPUs (General Purpose Graphics Processing Units), has improved by far the effectiveness and the performance of SW. The availability of multiple processing units and of light synchronization mechanisms on one side, and the easiness of reuse and adaptation of software compared to hardware, make software a viable alternative. In this context, Sara Vinco proposes a range of methodologies that, from a common starting point, gain C++ code generation with different approaches. The starting point is a set of heterogeneous existing components, reconciliated to a single formalism through the UNIVERCM-based approach. The first approach proposed is the generation of C++ code implementing the starting functionality. The generated code can be used both as an efficient implementation of the starting system, or rather as a software version of its functionality. The generated components are converted to one or more C++ functions, managed by a single scheduling routine. The implementation of the scheduling routine differs whether the support of continuous time behaviors is preserved [IC.18] or not [IC.6]. The generated code can also be parallelized by 6
creating local schedulers, associated with different execution cores and managing a subset of the C++ functions. A centralized scheduler is in charge of synchronizing local schedulers [IC.11]. GP-GPUs offer a massive level of parallelism that can be exploited to speed up computation. In detail, discrete GP-GPUs can be used to run code that simulates the starting system, while integrated GP-GPUs (or APUs) can be exploited as hardware accelerators for running software code. Sara Vinco proposed two flows, targeting each of such scenarios. SAGA proposed a flow to simulate RTL HDL code on GP-GPUs. RTL processes are partitioned in dataflows according to inter-process dependencies, and such dataflows are then associated with different cores. Multiple copies of the same dataflow can be run in parallel to increase throughput and to run more instancies at one time [IC.12], [IC.17], [IC.14]. Generating code for APUs allows to modify the internal structure of the code, in order to get more performing code. To this extent, [IC.19] proposed an approach to exploit both inter-process dependencies and pipeline structure of the starting designs to achieve massively parallel execution in software on APUs. The code generation flows have been accompanied by the implementation of an efficient data type library, reproducing hardware data types (e.g., multi-value logic) in a very efficient and performing way. This allows to preserve compatibility with respect to the starting code, without slowing down the execution or adding the overhead of hardware libraries (e.g., SystemC) [JR.2], [IC.7]. 7
Page 1 and 2: Sara Vinco Name Sara Vinco Date of
Page 3 and 4: PRESENTATIONS AND POSTER SESSIONS
Page 5: Professional Activities • Co-chai
Page 9: IC.12. IC.11. IC.10. IC.9. IC.8. IC

Curriculum vitae (pdf, en, 50 KB, 10/23/13)

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