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34 4 X <br />
pixel 498 µm<br />
chip 1.3 × 2.5 cm 2<br />
24 × 48<br />
<br />
50 µW/pixel ( 50 mW/chip)<br />
2 %(5.5 %)<br />
FWHM: 300 eV (@ 0 pF)(10 %)<br />
4.1: Caltech ASIC <br />
4.4 – 4.5 <br />
100 ns 30 µs 16 <br />
1µs <br />
1 µs <br />
<br />
8 µs ASIC <br />
ADC <br />
4.6 ASIC <br />
DSP <br />
<br />
4.2.4.3 <br />
Caltech ASIC (Charge Sharing) <br />
ASIC <br />
8 9 <br />
() 18 2 <br />
<br />
<br />
<br />
1 18 <br />
× 16 288 ADC A/D 12bit ADC <br />
0.5KBytes <br />
4.2.5 <br />
Caltech ASIC <br />
<br />
<br />
1. <br />
<br />
1.0 %<br />
2 2 <br />
10 3 5