T-51750GD065J-FW-ADN - OLED-LCD-TFT

[Note]
A) Power and signals sequence:
t1 ≤ 10 ms 200 ms < t6
3.0V or 4.5V
0.3V
0 < t2 ≤ 50 ms 0 ≤ t7
0 < t3 ≤ 50 ms
0 < t4 ≤ 50 ms
500 ms < t5
VCC-dip conditions:
1) When 2.4 V ≤ VCC < 3.0 V, td ≤ 10 ms
2) When VCC < 2.4 V
VCC-dip conditions should also follow the power and signals sequence.
B) Typical current condition:
64- gray- bar-pattern
480 line mode
VCC = +3.3 V, f H=31.5kHz, f V=60Hz, f CLK= 25MHz
VCC = +5.0 V, f H=31.5kHz, f V=60Hz, f CLK= 25MHz
C) For typical luminance of 400 cd/m 2
VCC
data
t1 t2 t3
Backlight
3.0V or 4.5V
t4 t5
t6 t7
data: RGB DATA, DCLK, HD, VD, DENA
td
0.3V 0.3V
T-51750GD065J-FW-ADN (AD) No. 2005-0498 OPTREX CORPORATION Page 4/24
2.4 V
3.0 V or 4.5V
VCC