IUP GEII - Abcelectronique

UFR SCIENCES 

REIMS 

IUP GEII 

OPTION MCI 

DOCUMENTS DE COURS 

(fascicule autorisé lors des contrôles) 

M. Deloizy 

Édition du 14/09/2005 

http://michel.deloizy.free.fr

Chronogrammes du 6809 (Motorola) 

6809 - 2 -

Circuits périphériques - 3 - 

UVPROM Am27C64 (8k x 8)

HN58S65AI (EEPROM) 

Circuits périphériques - 4 -

HM65764 (RAM statique) 

Circuits périphériques - 5 -

TL16C450 (Communication série) 

Brochage, Chronogrammes 


Description des signaux 

A0 

A1 

A2 

I 

Register select. A0, A1, and A2 are three inputs used during read and write operations to select the 

ACE register to read from or write to. Refer to Table 1 for register addresses, also refer to the 

address strobe ( ADS ) signal description. 

ADS I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip 

select signals (CS0, CS1, CS 2 ) drive the internal select logic directly; when high, the register select 

and chip select signals are held in the state they were in when the low-to-high transition of ADS 

occurred. 

BAUDOUT O Baud out. BAUDOUT is a16× clock signal for the transmitter section of the ACE. The clock rate is 

established by the reference oscillator frequency divided by a divisor specified by the baud generator 

divisor latches. 

BAUDOUT may also be used for the receiver section by tying this output to the RCLK input. 

CS0, CS1, 

CS 2 

I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the 

ADS signal description.


CSOUT O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select 

inputs (CS0, CS1, and CS 2 ). CSOUT is low when the chip is deselected. 

CTS I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of 

the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has 

changed states since the last read from the modem status register. If the modem status interrupt is 

enabled when CTS changes state, an interrupt is generated. 

D0 – D7 I/O Data bus. D0 – D7 are 3-state data lines that provide a bidirectional path for data, control, and status 

information between the ACE and the CPU. 

DCD I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 

(DCD) of the modem status register. Bit 3 (DDCD) of the modem status register indicates that this 

signal has changed states since the last read from the modem status register. If the modem status 

interrupt is enabled when the DCD changes state, an interrupt is generated. 

DDIS O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can 

disable an external transceiver. 

DISTR 

DIS TR 

I Data input strobes. When either DISTR or DIS TR is active (high or low respectively) while the ACE 

is selected, the CPU is allowed to read status information or data from a selected ACE register. Only 

one of these inputs is required for the transfer of data during a read operation. The other input should 

be tied in its inactive state (i.e., DISTR tied low or DIS TR tied high). 

DOSTR 

DOS TR 

I Data output strobes. When either DOSTR or DOS TR is active (high or low respectively), while the 

ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. 

Only one of these inputs is required to transfer data during a write operation. The other input should 

be tied in its inactive state (i.e., DOSTR tied low or DOS TR tied high). 

DSR I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) 

of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal 

has changed state since the last read from the modem status register. If the modem status interrupt is 

enabled when the DSR changes state, an interrupt is generated. 

D TR O Data terminal ready. When active (low), D TR informs a modem or data set that the ACE is ready to 

establish communication. DTR 

is placed in the active state by setting the DTR bit of the modem 

control register to a high level. D TR is placed in the inactive state either as a result of a master reset 

or during loop mode operation or clearing bit 0 (DTR) of the modem control register. 

INTRPT O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be 

serviced. The four conditions that cause an interrupt are: a receiver error, received data is available, 

the transmitter holding register is empty, or an enabled modem status interrupt. The INTRPT output 

is reset (inactivated) either when the interrupt is serviced or as a result of a master reset. 

MR I Master reset. When active (high), MR clears most ACE registers and sets the state of various output 

signals. 

Refer to Table 2 for ACE reset functions. 

OUT 1 

OUT 2 

O Outputs 1 and 2. OUT 1 and OUT2 

are user-designated output terminals that are set to their active 

states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT 1 and 

OUT 2 are set to their inactive (high) states as a result of master reset or during loop mode operations 

or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. 

RCLK I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE. 

RI I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the 

modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input has 

transitioned from a low to a high state since the last read from the modem status register. If the 

modem status interrupt is enabled when this transition occurs, an interrupt is generated. 

RTS O Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit 

data. RTS is set to its active state by setting the RTS modem control register bit and is set to its 

inactive (high) state either as a result of a master reset or during loop mode operations or by clearing 

bit 1 (RTS) of the MCR. 

SIN I Serial input. SIN is the serial data input from a connected communications device. 

SOUT O Serial output. SOUT is the composite serial data output to a connected communication device. 

SOUT is set to the marking (set) state as a result of MR. 

V CC 

5-V supply voltage 

V SS 

Supply common 

XTAL1 

XTAL2 

I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or 

crystal).


Autres circuits logiques 

Décodeurs démultiplexeurs 

74138 

74139

74139 


Buffers 

74244

74245 


Latches 

74373

Circuits périphériques 11 

AD7918 (Analog Devices) 

Pin Mnemonic Description 

1 VREF Reference Input, 1.2 V to VDD. 

2 VIN Analog Input, 0 V to VREF. 

3 GND Analog and Digital Ground. 

4 CONVST# 

Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an 

internally generated CONVST# signal. A high-to-low transition on this line initiates 

the conversion process if the internal CONVST# signal is low. Depending on the 

signal on this pin at the end of a conversion, the AD7819 automatically powers 

down. 

5 CS# Chip Select. This is a logic input. CS# is used in conjunction with RD# to enable 

outputs. 

6 RD# Read Pin. This is a logic input. When CS# is low and RD# goes low, the DB7– 

DB0 leave their high impedance state and data is driven onto the data bus. 

7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the 

conversion process. 

8– DB0–DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible. 

15 

16 VDD Positive power supply voltage, 2.7 V to 5.5 V. 

Parameter VDD= 5 V ± 10% Unit Conditions/Comments 

tPOWER-UP 

1.5 µs (max) Power-Up Time of AD7819 after Rising Edge of CONVST. 

t1 4.5 µs (max) Conversion Time. 

t2 30 ns (min) CONVST# Pulsewidth. 

t3 30 ns (max) CONVST# Falling Edge to BUSY Rising Edge Delay. 

t4 0 ns (min) CS# to RD# Setup Time. 

t5 0 ns (min) CS# Hold Time after RD# High. 

t6 10 ns (max) Data Access Time after RD# Low. 

t7 10 ns (max) Bus Relinquish Time after RD# High. 

t8 100 ns (min) Data Bus Relinquish to Falling Edge of CONVST# Delay.

C167CR - 12 - 

C167CR 

Cette partie contient une documentation réduite du C167CR (Infineon), du compilateur C (Tasking) et 

des systèmes matériels étudiés (TQ tech.). 

Les informations et les graphes sont tous issus et recopiés à partir des documents techniques originaux. 

Certaines parties sont traduites, d'autres sont restées intentionnellement dans leur langue d'origine 

(l'anglais), qu'il est nécessaire de maîtriser afin de pouvoir mettre en œuvre les technologies actuelles. 

M. Deloizy

Présentation C167CR - 13 - 

Présentation 

Famille C166 

Versions du C167 

→ SAK-C167CR-16RM


Architecture interne 

High Performance 16-bit CPU with four stage Pipeline 

• 80/60 ns minimum instruction cycle time, with most instructions executed in 1 cycle 

• 400/300 ns multiplication (16-bit x 16-bit), 800/600 ns division (32-bit/16-bit) 

• Multiple high bandwidth internal data buses 

• Register based design with multiple variable register banks 

• Single cycle context switching support 

• 16 MBytes linear address space for code and data (Von Neumann architecture) 

• System stack cache support with automatic stack overflow/underflow detection 

Control Oriented Instruction Set with High Efficiency 

• Bit, byte, and word data types 

• Flexible and efficient addressing modes for high code density 

• Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and 

user defined flags 

• Hardware traps to identify exception conditions during runtime 

• High Level Language support for semaphore operations and efficient data access 

Integrated On-chip Memory 

• 2 KByte internal RAM for variables, register banks, system stack and code 

• 2 KByte on-chip high-speed XRAM for variables, user stack and code (not on all derivatives) 

• 128 KByte or 32 KByte on-chip ROM (not for ROMless devices) 

External Bus Interface 

• Multiplexed or demultiplexed bus configurations 

• Segmentation capability and chip select signal generation 

• 8-bit or 16-bit data bus 

• Bus cycle characteristics selectable for five programmable address areas


16-Priority-Level Interrupt System 

• 56 interrupt nodes with separate interrupt vectors 

• 240/180 ns typical interrupt latency (400/300 ns maximum) in case of internal program execution 

• Fast external interrupts 

8-Channel Peripheral Event Controller (PEC) 

• Interrupt driven single cycle data transfer 

• Transfer count option (std. CPU interrupt after programmable number of PEC transfers) 

• Eliminates overhead of saving and restoring system state for interrupt requests 

Intelligent On-chip Peripheral Subsystems 

• 16-channel 10-bit A/D Converter with programmable conversion time (7.76 ms minimum), auto 

scan modes, channel injection mode 

• Two 16-channel Capture/Compare Units with 2 independent time bases each, very flexible PWM 

unit/event recording unit with different operating modes, includes four 16-bit timers/counters, 

maximum resolution fCPU/8 

• 4-channel PWM unit 

• Two Multifunctional General Purpose Timer Units 

GPT1: Three 16-bit timers/counters, maximum resolution fCPU/8 

GPT2: Two 16-bit timers/counters, maximum resolution fCPU/4 

• Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, 

and overrun error detection 

• High Speed Synchronous Serial Channel programmable data length and shift direction 

• On-chip CAN Bus Module, Rev. 2.0B active (not on all derivatives) 

• Watchdog Timer with programmable time intervals 

• Bootstrap Loader for flexible system initialization 

111 IO Lines with Individual Bit Addressability 

• Tri-stated in input mode 

• Selectable input thresholds (not 

on all pins) 

• Push/pull or open drain output 

mode 

• Programmable port driver control 

(fast/reduced edge) 

Different Temperature Ranges 

• 0 to + 70 °C, – 40 to + 85 °C, – 

40 to + 125 °C 

Infineon CMOS Process 

• Low power CMOS technology 

including power saving Idle and 

Power Down modes. 

144-pin Plastic Metric Quad Flat 

Pack (MQFP) Package 

• P-MQFP, 28 x 28 mm body, 0.65 

mm (25.6 mil) lead spacing, 

surface mount technology

Organisation mémoire C167CR - 16 - 

Organisation mémoire 

Architecture Von Neumann 

Espace mémoire unique pour ROM interne, RAM interne, SFRs, périphériques internes et mémoire 

externe. 

16 M-octets adressables 

- 256 segments de 64 Ko chacun 

- chaque segment est divisé en 4 pages de 16 Ko 

Mémoire interne essentiellement située dans le segment 0. 

• 0000h … 7FFFh : ROM / Flash ou OTP interne. 

Peut être déplacé en 10000h … 1FFFFh pour permettre ROM externe en adresse 

basse. 

• F000h … FFFFh : RAM interne et SFRs 

Code exécutable dans toute zone mémoire (RAM ou ROM), sauf dans les SFRs. 

Octets situés en adresses paires ou impaires. 

Mots (16 bits) situés en adresse paire (MSB en adresse impaire). 

Longs mots (32 bits) rangés comme 2 mots consécutifs (LSB en adresse paire). 

Bits adressables pour certains SFRs, une partie de la RAM interne et registres à usage général.


RAM interne et SFR 

2 Ko de IRAM, 256 octets de SFRs 

Mémoire XRAM 

2 Ko. Mémoire interne située en page 3. 

Accessible comme RAM externe (sans utiliser les bus externes). 

Peut être désactivée par bit XPEN de SYSCON. 

Pas de Wait-states 

Accessible de l'extérieur en DMA


Registres à usage général 

(registres de travail) 

Blocs de 16 mots consécutifs en RAM interne. 

Registre CP (Context Pointer) indique l'adresse de base de la banque de registres active. 

Internal RAM Address Byte Registers Word Register 

+ 1EH – R15 

+ 1CH – R14 

+ 1AH – R13 

+ 18H – R12 

+ 16H – R11 

+ 14H – R10 

+ 12H – R9 

+ 10H – R8 

+ 0EH RH7 RL7 R7 

+ 0CH RH6 RL6 R6 

+ 0AH RH5 RL5 R5 

+ 08H RH4 RL4 R4 

+ 06H RH3 RL3 R3 

+ 04H RH2 RL2 R2 

+ 02H RH1 RL1 R1 

+ 00H RH0 RL0 R0 

→ Permet commutation de contexte rapide par modification de CP. 

Instruction SCXT (Switch Context) réalise la commutation de banques et une sauvegarde automatique du 

contexte précédent. 

Mémoire externe 

4 tailles de banques mémoires possibles : 

- 64 Ko. Mode non segmenté. A15…A0 sur P0 et P1 

- 256 Ko. Mode segmenté 2 bits. A17,A16 sur P4 ; A15…A0 sur P0 et P1 

- 1 Mo. Mode segmenté 4 bits. A19…A16 sur P4 ; A15…A0 sur P0 et P1 

- 16 Mo. Mode segmenté 8 bits. A22…A16 sur P4 ; A15…A0 sur P0 et P1 

4 types de bus différents : 

bus adresses données 

multiplexé 16 bits P0 P0 (par défaut après RESET) 

multiplexé 8 bits P0 P0:7…0 

démultiplexé 16 bits P1 P0 

Démultiplexé 8 bits P1 P0:7…0 

Le modèle de mémoire et le type de bus est sélectionné pendant le RESET en agissant sur EA# et P0. 

Les adressages de bits ne sont pas possibles en mémoire externe.

CPU C167CR - 19 - 

CPU 

(Central Processing Unit) 

Architecture 

- ALU 16 bits 

- Pipeline à 4 étages (parallélisme) 

- Accès aux périphériques externes par EBC (External Bus Controller). Le CPU peut 

continuer à fonctionner en attendant que EBC effectue un accès externe. 

- Périphériques internes utilisent un générateur d'horloge distinct. 

- Contrôleur d'interruption intégré avec gestion des priorités. 

- Traitement d'interruptions par PEC (Peripheral Event Controller) 

- Interruptions logicielles, NMI traitées comme iT ordinaires 

- Watchdog 

- Modes faible consommation 

États CPU particuliers : 

- Reset : force le CPU dans un état prédéfini 

- IDLE : horloge du CPU arrêtée ; horloges des périphériques actives 

- POWER-DOWN : Toutes horloges arrêtées. Entrées des périphériques ignorées. 

Sortie du mode IDLE : par interruption 

Sortie du mode POWER-DOWN : par RESET

CPU C167CR - 20 - 

Pipeline 

Instruction exécutée en 4 étapes → 4 étages du pipeline fonctionnant simultanément. 

1. Recherche de l'instruction 

2. Décodage de l'instruction, calcul des adressages, récupération des éventuels opérandes 

3. Exécution de l'instruction. Utilisation de l'ALU. Mise à jour de PSW. 

4. Écriture des résultats dans RAM interne ou externe. 

Fonctionnement parallèle : 

Cycle machine 

FETCH I 1 I 2 I 3 I 4 I 5 I 6 

DECODE I 1 I 2 I 3 I 4 I 5 

EXECUTE I 1 I 2 I 3 I 4 

WRITEBACK I 1 I 2 I 3 

→ Beaucoup d'instructions s'exécutent en 1 cycle machine. 

Problèmes liés au pipeline : 

4 instructions traitées simultanément ⇒ risque de mauvaise exécution dans certains cas. 

→ le C167 insère parfois une "instruction injectée" dans le deuxième étage du pipeline quand une 

instruction ne peut pas être traitée complètement en 1 cycle. 

Exemple du branchement conditionnel : une instruction injectée est utilisée pour déterminer l'instruction 

désignée par le branchement. 

Certains cas nécessitent l'attention du programmeur : 

• Modification du contexte (changement de banque de registres) 

SCXT CP,#0FC00h ;sélection d'un nouveau contexte 

… 

;ne doit pas utiliser un registre (car ancien contexte encore actif) 

MOV R0,#data ;écrit data dans registre R0 du nouveau contexte 

• Modification du pointeur de page de données 

MOV DPP0,#4 ;sélection de la page de donnée 4 

… 

;ne doit pas utiliser une instruction utilisant DPP0 

MOV DPP0:0000H,R1 ;écrit R1 à l'adresse 10000H 

• Modification de la pile système 

MOV SP,#0FA40H ;définit un nouveau sommet de pile système 

… 

;ne doit pas utiliser d'instruction type POP,RET,… 

;PUSH,CALL,SCXT autorisés car résolus en interne 

POP R0 

;dépile R0 à partir de la nouvelle pile 

• Contrôle des interruptions 

IEN ou ILVL de PSW non pris en compte instantanément : 

BCLR IEN 

;désactive interruptions 

… 

;instruction encore interruptible 

… 

;interruptions désactivées (début d'une séquence critique) 

… 

BSET IEN 

;autorise interruptions (fin de la séquence critique) 

ou : 

ATOMIC #3 

;désactive immédiatement les interruptions 

BCLR IEN 

;interdit les interruptions 

… 

;séquence critique 

BSET IEN

CPU C167CR - 21 - 

• Initialisation des ports 

incorrect : 

BSET DP3.12 ;met le bit 12 de P3 en sortie 

BSET P3.9 ;P3.12 est encore une entrée ; rd/mod/wr lit P3.12 

correct : 

BSET DP3.12 

NOP 

BSET P3.9 ;P3.12 est en sortie ; rd/mod/wr lit le latch de la sortie P3.12 

Opérations sur bits 

Utilisent des cycles Lecture/Modification/Écriture sur octets. 

Actives uniquement sur les zone adressables par bits (RAM interne, SFRs). 

Pile système 

‣ utilisation des sous programmes 

‣ gestion des interruptions 

‣ sauvegardes gérées par le CPU 

• Pile de type LIFO 

• Utilise le registre SP (Stack Pointer) 

• SP évolue vers les adresses basses quand une donnée est rangée dans la pile. 

• Seules les données 16 bits sont autorisées. 

• STKOV et STKUN sont des registres qui permettent de contrôler les dépassements de pile. 

Ils permettent également la gestion d'une pile circulaire.

SFRs C167CR - 22 - 

SFRs (Special Function Registers) 

XPER-SHARE 

VISIBLE 

XPEN 

BDRSTEN 

OWDDIS 

CSCFG 

WRCFG 

CLKEN 

BYTDIS 

ROMEN 

SGTDIS 

ROMS1 

STKSZ 

XBUS Peripheral Share Mode Control 

0: External accesses to XBUS peripherals are disabled 

1: XBUS peripherals are accessible via the external bus during hold mode 

Visible Mode Control 

0: Accesses to XBUS peripherals are done internally 

1: XBUS peripheral accesses are made visible on the external pins 

XBUS Peripheral Enable Bit 

0: Accesses to the on-chip X-Peripherals and their functions are disabled 

1: The on-chip X-Peripherals are enabled and can be accessed 

Bidirectional Reset Enable Bit 

0: Pin RSTIN is an input only. 

1: Pin RSTIN is pulled low during the internal reset sequence after any reset. 

Oscillator Watchdog Disable Bit (Cleared after reset) 

0: The on-chip oscillator watchdog is enabled and active. 

1: The on-chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator 

input. 

Chip Select Configuration Control (Cleared after reset) 

0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins 

synchronously. 

1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the 

(enabled) port pins. 

Write Configuration Control (Set according to pin P0H.0 during reset) 

0: Pins WR and BHE retain their normal function 

1: Pin WR acts as WRL, pin BHE acts as WRH 

System Clock Output Enable (CLKOUT, cleared after reset) 

0: CLKOUT disabled: pin may be used for general purpose IO 

1: CLKOUT enabled: pin outputs the system clock signal 

Disable/Enable Control for Pin BHE (Set according to data bus width) 

0: Pin BHE enabled 

1: Pin BHE disabled, pin may be used for general purpose IO 

Internal ROM Enable (Set according to pin EA during reset) 

0: Internal program memory disabled, accesses to the ROM area use the external bus 

1: Internal program memory enabled 

Segmentation Disable/Enable Control (Cleared after reset) 

0: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) 

1: Segmentation disabled (Only IP is saved/restored) 

Internal ROM Mapping 

0: Internal ROM area mapped to segment 0 (00’0000H … 00’7FFFH) 


System Stack Size 

Selects the size of the system stack (in the internal RAM) from 32 to 512 words 

Stack Size (words) Internal RAM Addresses (words) 

0 0 0 256 00’FBFE … 00’FA00 (Default after Reset) 

0 0 1 128 00’FBFE … 00’FB00 

0 1 0 64 00’FBFE … 00’FB80 

0 1 1 32 00’FBFEH … 00’FBC0H 

1 0 0 512 00’FBFEH … 00’F800H 

1 0 1 – Reserved. Do not use this combination. 

1 1 0 – Reserved. Do not use this combination. 

1 1 1 1024 00’FDFEH … 00’F600H (Note: No circular stack)

SFRs C167CR - 23 - 

N 

C 

V 

Z 

E 

MULIP 

USR0 

HLDEN, 

ILVL, 

IEN 

Negative Result 

Set, when the result of an ALU operation is negative. 

Carry Flag 

Set, when the result of an ALU operation produces a carry bit. 

Overflow Result 

Set, when the result of an ALU operation produces an overflow. 

Zero Flag 

Set, when the result of an ALU operation is zero. 

End of Table Flag 

Set, when the source operand of an instruction is 8000H or 80H. 

Multiplication/Division In Progress 

0: There is no multiplication/division in progress 

1: A multiplication/division has been interrupted 

User General Purpose Flag May be used by the application software. 

Interrupt and EBC Control Fields 

Define the response to interrupt requests and enable external bus arbitration. 

En mode non segmenté, CSP est ignoré.

SFRs C167CR - 24 - 

Pointeurs de pages de données (DDPx) 

→ Sélection simultanée de 4 pages de données de 16 Ko dans l'ensemble de la mémoire.

SFRs C167CR - 25 - 

Pointeur de contexte (CP) 

→ Indique l'adresse de base du bloc de registres (GPR : General Purpose Registers) en RAM interne. 

Pointeur de Pile (SP) 

Poids fort Multiplication/Division (MDH) 

- 16x16→32 : 16 bits poids fort du résultat 

- 32:16→16+reste(16) : MDH contient 16 bits poids fort du dividende. Après la division, 

MDH contient le reste. 

Quand interruption, MDH doit être sauvegardé.

SFRs C167CR - 26 - 

Poids faible Multiplication/Division (MDL) 

Contrôle des multiplications/divisions 

MDRIU Multiply/Divide Register In Use 

0 : Cleared when register MDL is read via software 

1 : Set when register MDL or MDH is set via software, or when a multiply or divide 

instruction is executed. 

!! Internal Machine Status 

The multiply/divide unit uses these bits to control internal operations. Never modify these bits 

without saving and restoring register MDC 

Zéros et Uns

Interruptions C167CR - 27 - 

Interruptions 

‣ 56 sources d'interruption 

‣ 16 niveaux de priorité 

Quand une interruption est demandée : 

• l'exécution du programme est suspendue 

• l'état du programme courant est sauvegardé : IP, PSW et CSP (en mode segmenté) empilés 

• l'interruption la plus prioritaire est prise en compte 

• la routine d'interruption est exécutée 

• quand l'instruction RETI est trouvée, le contexte initial (IP, PSW et CSP) est récupéré et 

l'exécution du programme peut continuer. 

Une interruption sera prise en compte par le CPU si : 

- le flag IEN de PSW est à 1 

- le niveau de priorité de l'interruption demandée est supérieur à celui du CPU (indiqué dans 

PSW). 

Sources et vecteurs d'interruption 

Source of Interrupt or 

PEC Service Request 

Request 

Flag 

Enable 

Flag 

Interrupt 

Vector 

Vector 

Location 

Trap 

Number 

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040H 10H/16D 



CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004CH 13H/19D 




CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005CH 17H/23D 



CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068H 1AH/26D 

CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006CH 1BH/27D 

CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070H 1CH/28D 

CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074H 1DH/29D 

CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078H 1EH/30D 

CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007CH 1FH/31D 

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0H 30H/48D 



CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCH 33H/51D 

CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0H 34H/52D 



CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCH 37H/55D 

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0H 38H/56D 

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4H 39H/57D 

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8H 3AH/58D 

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECH 3BH/59D 

CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0H 3CH/60D 

CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110H 44H/68D




CAPCOM Timer 0 T0IR T0IE T0INT 00’0080H 20H/32D 

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084H 21H/33D 

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4H 3DH/61D 

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8H 3EH/62D 

GPT1 Timer 2 T2IR T2IE T2INT 00’0088H 22H/34D 

GPT1 Timer 3 T3IR T3IE T3INT 00’008CH 23H/35D 




GPT2 CAPREL Register CRIR CRIE CRINT 00’009CH 27H/39D 

A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0H 28H/40D 

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4H 29H/41D 

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H 2AH/42D 

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH 47H/71D 

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH 2BH/43D 

ASC0 Error S0EIR S0EIE S0EINT 00’00B0H 2CH/44D 

SSC Transmit SCTIR SCTIE SCTINT 00’00B4H 2DH/45D 

SSC Receive SCRIR SCRIE SCRINT 00’00B8H 2EH/46D 

SSC Error SCEIR SCEIE SCEINT 00’00BCH 2FH/47D 

PWM Channel 0 … 3 PWMIR PWMIE PWMINT 00’00FCH 3FH/63D 

CAN1 XP0IR XP0IE XP0INT 00’0100H 40H/64D 

Unassigned node XP1IR XP1IE XP1INT 00’0104H 41H/65D 

Unassigned node XP2IR XP2IE XP2INT 00’0108H 42H/66D 

PLL/OWD XP3IR XP3IE XP3INT 00’010CH 43H/67D 

Exception Condition Trap Flag Trap 

Vector 

Vector 

Location 

Trap 

Number 

Trap 

Prior. 

Reset Functions 

Hardware Reset RESET 00’0000H 00H III 

Software Reset RESET 00’0000H 00H III 

Watchdog Timer Overflow RESET 00’0000H 00H III 

Class A Hardware Traps 

Non-Maskable Interrupt NMI NMITRAP 00’0008H 02H II 

Stack Overflow STKOF STOTRAP 00’0010H 04H II 

Stack Underflow STKUF STUTRAP 00’0018H 06H II 

Class B Hardware Traps 

Undefined Opcode UNDOPC BTRAP 00’0028H 0AH I 

Protected Instruction Fault PRTFLT BTRAP 00’0028H 0AH I 

Illegal Word Operand Access ILLOPA BTRAP 00’0028H 0AH I 

Illegal Instruction Access ILLINA BTRAP 00’0028H 0AH I 

Illegal External Bus Access ILLBUS BTRAP 00’0028H 0AH I 

Reserved 

[2CH- 

3CH] 

[0BH-0FH] 

Software Traps 

TRAP Instruction 

Any 

[00’0000H- 

00’01FCH] 

in steps of 

4H 

Any [00H- 

7FH] 

Current 

CPU 

Priority


Registres de contrôle des interruptions 

Même structure pour toutes les sources d'interruption : 

Bit 

GLVL 

ILVL 

xxIE 

xxIR 

Function 

Group Level 

Defines the internal order for simultaneous requests of the same priority. 

3: Highest group priority 

0: Lowest group priority 

Interrupt Priority Level 

Defines the priority level for the arbitration of requests. 

FH: Highest priority level 

0H: Lowest priority level 

Interrupt Enable Control Bit (individually enables/disables a specific source) 

‘0’: Interrupt request is disabled 

‘1’: Interrupt Request is enabled 

Interrupt Request Flag 

‘0’: No request pending 

‘1’: This source has raised an interrupt request 

Gestion des priorités 

Les priorités sont gérées par ILVL et GLVL. 

Si deux interruptions de même niveau sont demandées simultanément, celle dont le niveau défini dans 

GLVL est supérieur sera prise en compte en premier. 

Important : 

- Il ne doit pas y avoir 2 interruptions définies avec à la fois des ILVL et GLVL identiques. 

- Une interruption de niveau 0 ne pourra pas être prise en compte par le CPU. 

Interruptions externes : 

Le C167CR n'a pas de pattes dédiées aux interruptions (de type INTR ou IRQ). 

→ Des pattes d'entrée de périphériques sont utilisées à cet effet : 

Port Pin Original Function Control Register 

P7.7-4/CC31-28IO CAPCOM register 31-28 capture input CC31-CC28 

P1H.7-4/CC27-24IO CAPCOM register 27-24 capture input CC27-CC24 



P3.7/T2IN Auxiliary timer T2 input pin T2CON 

P3.5/T4IN Auxiliary timer T4 input pin T4CON 

P3.2/CAPIN GPT2 capture input pin T5CON


Traps 

Les traps déclenchent une procédure d'interruption avec un mécanisme similaire aux interruptions 

déclenchées par les périphériques. 

Deux types de Traps : 

- traps logiciels 

Utilisent l'instruction TRAP suivi d'un opérande correspondant à un vecteur d'interruption (entre 

0000H et 01FCH). 

Exécutent le programme d'interruption associé (comme si un périphérique l'avait provoqué). Les 

flags d'interruption (dans xxIC) ne sont cependant pas affectés. 

Le niveau de priorité du CPU dans PSW n'est pas modifié par un trap logiciel. 

- traps matériels 

Sont déclenchés automatiquement à la suite d'incidents ou d'états spécifiques du système lors de 

l'exécution du programme. 

Ils sont non masquables et ont toujours une priorité supérieure à celle du CPU. Si plusieurs traps 

matériels sont demandés simultanément, celui de plus forte priorité sera pris en compte en 

premier. 

Ils se divisent en deux classes : 

- traps de classe A : NMI, débordements de pile système. Ces traps ont la même priorité, 

mais des vecteurs différents 

- traps de classe B : code opérateur indéfini, faute de protection, accès illégal à un mot, 

accès illégal au bus externe. Ces traps ont la même priorité, mais un vecteur unique. On peut 

connaître la cause de déclenchement du trap en consultant le registre TFR. 

Bit 

ILLBUS 

ILLINA 

ILLOPA 

PRTFLT 

UNDOPC 

STKUF 

STKOF 

NMI 

Function 

Illegal External Bus Access Flag : An external access has been attempted with no 

external bus defined. 

Illegal Instruction Access Flag : A branch to an odd address has been attempted. 

Illegal Word Operand Access Flag : A word operand access (read or write) to an odd 

address has been attempted. 

Protection Fault Flag : A protected instruction with an illegal format has been 

detected. 

Undefined Opcode Flag : The currently decoded instruction has no valid C167CR 

opcode. 

Stack Underflow Flag : The current stack pointer value exceeds the content of register 

STKUN. 

Stack Overflow Flag : The current stack pointer value falls below the content of reg. 

STKOV. 

Non Maskable Interrupt Flag : A negative transition (falling edge) has been detected 

on pin NMI. 

Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be requested 

after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had 

been set by hardware.

Ports parallèles C167CR - 31 - 

Ports parallèles 

Bit 

PxLIN 

PxHIN 

Function 

Portx Low Byte Input Level Selection 

0: Pins Px.7 … Px.0 switch on standard TTL input levels 

1: Pins Px.7 … Px.0 switch on special threshold input levels 

Portx High Byte Input Level Selection 

0: Pins Px.15 … Px.8 switch on standard TTL input levels 

1: Pins Px.15 … Px.8 switch on special threshold input levels 

Bit 

Function 

BIPEC Bus Interface Pins Edge Characteristic (Defines the outp. rise/fall time t RF ) 

0: Fast edge mode, rise/fall times depend on the driver’s dimensioning. 

1: Reduced edge mode. 

BIPEC controls: PORT0, PORT1, Port4, Port 6, RD, WR, ALE, CLKOUT, 

BHE/WRH, READY (emulation mode only). 

NBPEC Non-Bus Pins Edge Characteristic (Defines the output rise/fall time t RF ) 

0: Fast edge mode, rise/fall times depend on the driver’s dimensioning. 

1: Reduced edge mode. 

NBPEC controls: Port2, Port3, Port7, Port8, RSTOUT, RSTIN 

(bidirectional reset mode only). 

Fonctions alternées 

Port Alternate Function(s) Alternate Signal(s) 

PORT0 Address and data lines when accessing 

AD15 … AD0 

external resources (e.g. memory) 

PORT1 Address lines when accessing ext. resources 

Capture inputs of the CAPCOM units 

A15 … A0, 

CC27IO … CC24IO 

Port2 Capture inputs or compare outputs of the CAPCOM units, 

CAPCOM timer input 

Fast external interrupt inputs 

CC15IO … CC0IO, 

T7IN, 

EX7IN … EX0IN 

Port3 

System clock output 

Optional bus control signal 

Input/output functions of serial interfaces, 

timers 

CLKOUT, BHE/WRH, 

RxD0, TxD0, MTSR, MRST, 

SCLK, T2IN, T3IN, T4IN, 

T3EUD, T3OUT, CAPIN, 

T6OUT, T0IN


Port4 Selected segment address lines in systems with more than 

64 KBytes of external resources 

CAN interface (where implemented) 

A23 … A16, 

CAN1_TxD, CAN1_RxD 

Port5 Analog input channels to the A/D converter 

Timer control signal inputs 

AN15 … AN0, 

T2EUD, T4EUD, T5IN, T6IN 

Port6 Bus arbitration signals, 

Chip select output signals 

BREQ, HLDA, HOLD, 

CS4 … CS0 

Port_7 Capture inputs or compare outputs of the CAPCOM units 

PWM output signals 

CC31IO … CC28IO, 

POUT3 … POUT0 

Port8 Capture inputs or compare outputs of the CAPCOM units CC23IO … CC16IO 

Registres associés au port 0 

Port 16 bits bidirectionnel. 

Bit 

DP0X.y 

Function 

Port direction register DP0H or DP0L bit y 

DP0X.y = 0: Port line P0X.y is an input (high-impedance) 

DP0X.y = 1: Port line P0X.y is an output



Port 16 bits bidirectionnel. Fonctionnement identique à Port 0 

P1L : PORT1 Low Register SFR (FF04H/82H) Reset Value: - - 00H 

P1H : PORT1 High Register SFR (FF06H/83H) Reset Value: - - 00H 

DP1L : P1L Direction Ctrl. Register ESFR (F104H/82H) Reset Value: - - 00H 

DP1H : P1H Direction Ctrl. Register ESFR (F106H/83H) Reset Value: - - 00H 


Bit 

DP2.y 

Function 

Port direction register DP2 bit y 

DP2.y = 0: Port line P2.y is an input (high-impedance) 

DP2.y = 1: Port line P2.y is an output 

Bit 

ODP2.y 

Function 

Port2 Open Drain control register bit y 

ODP2.y = 0: Port line P2.y output driver in push/pull mode 

ODP2.y = 1: Port line P2.y output driver in open drain mode



Port 15 bits bidirectionnel. 

Bit 

DP3.y 

Function 

Port direction register DP3 bit y 

DP3.y = 0: Port line P3.y is an input (high-impedance) 

DP3.y = 1: Port line P3.y is an output 

Bit 

ODP3.y 

Function 

Port3 Open Drain control register bit y 

ODP3.y = 0: Port line P3.y output driver in push/pull mode 

ODP3.y = 1: Port line P3.y output driver in open drain mode 

Note: Due to pin limitations register bit P3.14 is not connected to an IO pin. 

Pins P3.15 and P3.12 do not support open drain mode. 


Port 8 bits bidirectionnel. Fonctionnement identique à Port 0 

P4 : Port4 Data Register SFR (FFC8H/E4H) Reset Value: - - 00H 

DP4 : P4 Direction Ctrl. Register SFR (FFCAH/E5H) Reset Value: - - 00H



Port 16 bits en entrée. 

Bit 

P5D.y 

Function 

Port5 Bit y Digital Input Control 

P5D.y = 0: Digital input stage connected to port line P5.y 

P5D.y = 1: Digital input stage disconnected from port line P5.y 

When being read or used as alternate input this line appears as ‘1’. 


Port 8 bits bidirectionnel. Fonctionnement identique à Port 2. 

P6 : Port6 Data Register SFR (FFCCH/E6H) Reset Value: - - 

DP6 : P6 Direction Ctrl. Register SFR (FFCEH/E7H) Reset Value: - - 00H 

ODP6 : P6 Open Drain Ctrl. Reg. ESFR (F1CEH/E7H) Reset value: - - 00H 



P7 : Port7 Data Register SFR (FFD0H/E8H) Reset Value: - - 00H 

DP7 : P7 Direction Ctrl. Register SFR (FFD2H/E9H) Reset Value: - - 00H 

ODP7 : P7 Open Drain Ctrl. Reg. ESFR (F1D2 /E9 ) Reset value: - - 00 



P8 : Port8 Data Register SFR (FFD4H/EAH) Reset Value: - - 00H 

DP8 : P8 Direction Ctrl. Register SFR (FFD6H/EBH) Reset Value: - - 00H 

ODP8 : P8 Open Drain Ctrl. Reg. ESFR (F1D6H/EBH) Reset Value: - - 00H

Timers C167CR - 36 - 

Timers 

→ GPT1 et GPT2 (General Purpose Timer) 

GPT1 : 3 timers/compteurs 16 bits avec une résolution maximale de 16 T CLK 

GPT2 : 2 timers/compteurs 16 bits avec une résolution maximale de 8 T CLK + capture/reload 16 bits 

Timer : utilise l'horloge interne 

Compteur : signaux externes pilotent 

l'unité de comptage 

GPT1 

→ T2, T3, T4 

→ fonctionnements identiques. Seul T3 

dispose d'une sortie. 

Contrôlés par T2CON, T3CON et 

T4CON. 

T2CON : Timer 2 Control Register SFR (FF40H/A0H) Reset value: 0000H 



TxCON : 

Bit 

TxI 

TxM 

TxR 

TxUD 

TxUDE 

Function 

Timer x Input Selection 

Depends on the Operating Mode, see respective sections. 

Timer x Mode Control (Basic Operating Mode) 

000 : Timer Mode 

001 : Counter Mode 

010 : Gated Timer with Gate active low 

011 : Gated Timer with Gate active high 

100 : T2,T4 : Reload Mode. T3 : Reserved. Do not use this combination. 

101 : T2,T4 : Capture Mode. T3 : Reserved. Do not use this combination. 

110 : Incremental Interface Mode 

111 : Reserved. Do not use this combination. 

Timer x Run Bit 

0 : Timer/Counter x stops 

1 : Timer/Counter x runs 

Timer x Up/Down Control 

Timer x External Up/Down Enable


T3OE 

Alternate Output Function Enable 

0: Alternate Output Function Disabled 

1: Alternate Output Function Enabled 

T3OTL Timer 3 Output Toggle Latch 

Toggles on each overflow/underflow of T3. Can be set or reset by software. 

Pin TxEUD Bit TxUDE Bit TxUD Count Direction 

X 0 0 Count Up 

X 0 1 Count Down 

0 1 0 Count Up 

1 1 0 Count Down 

0 1 1 Count Down 

1 1 1 Count Up 

Timer & Counter Modes : 

f 

TX 

= f 

CPU 

Txl 

8 ⋅ 2 

(timer mode) 

f < 

xIN 

f 

16 

CPU 

TxI Triggering Edge for Counter Increment/Decrement Tx 

0 0 0 None. Counter Tx is disabled 

0 0 1 Positive transition (rising edge) on TxIN 

0 1 0 Negative transition (falling edge) on TxIN 

T2, T3 et T4 

0 1 1 Any transition (rising or falling edge) on TxIN 

1 0 0 None. Counter Tx is disabled 

1 0 1 Positive transition (rising edge) of output toggle latch T3OTL 

1 1 0 Negative transition (falling edge) of output toggle latch T3OTL 

T2 & T4 

1 1 1 Any transition (rising or falling edge) of output toggle latch T3OTL 

Gated Timer with Gate active low or high : 

Timer mode + input clock gated by the external input pin TxIN (configured as input). 

Incremental Interface Mode : 

TxIN & TxEUD used to interface to an incremental encoder. 

Tx clocked by each transition on one or both of the external input pins which gives 2-fold or 4-fold 

resolution of the encoder input. 

Txl Triggering Edge for Counter Increment/Decrement 

0 0 0 None. Counter Tx stops. 

0 0 1 Any transition (rising or falling edge) on TxIN. 

0 1 0 Any transition (rising or falling edge) on TxEUD. 

0 1 1 Any transition (rising or falling edge) on any Tx input (TxIN or TxEUD). 

1 X X Reserved. Do not use this combination


Reload Mode (T2 & T4) : 

T3 reloaded with T2 or T4, triggered by TxIN or T3OTL (selected by Txl, as in counter mode). 

Note : When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of 

its run flag T2R or T4R. 

Capture Mode (T2 & T4) : 

T3 latched into Tx (T2 or T4) in response to a signal transition at TxIN. 

The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. 

Txl.0 et Txl.1 are used to select the active transition (as in counter mode) 

Txl.2 must be cleared. 

Note : When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independent 

of its run flag T2R or T4R. 

Interrupt Control for GPT1 Timers 

→ timer overflows from FFFFH to 0000H (when counting up) 

→ timer underflows from 0000H to FFFFH (when counting down


GPT2 

- T5 (auxiliaire) et T6 

(principal) 

- 16 bits 

- résolution maximale : 8 T CL 

- comptage et décomptage 

- registre de capture/reload 

16 bits (CAPREL) 

- concaténation possible de 

T5 sur T6 

- concaténation possible de 

l'unité Capture/compare sur 

T6 

Bit Function 

T6I Timer 6 Input Selection 


T6M Timer 6 Mode Control (Basic Operating Mode) 

000: Timer Mode 

001: Counter Mode 

010: Gated Timer with Gate active low 

011: Gated Timer with Gate active high 

1XX: Reserved. Do not use this combination. 

T6R Timer 6 Run Bit 

0: Timer/Counter 6 stops 

1: Timer/Counter 6 runs 

T6UD Timer 6 Up/Down Control (voir page 37) 

T6UDE Timer 6 External Up/Down Enable (voir page 37) 

T6OE Alternate Output Function Enable 

0: Alternate Output Function Disabled 

1: Alternate Output Function Enabled 

T6OTL Timer 6 Output Toggle Latch 

Toggles on each overflow/underflow of T6. Can be set or reset by software. 

T6SR Timer 6 Reload Mode Enable 

0: Reload from register CAPREL Disabled 

1: Reload from register CAPREL Enabled


Mode Timer : 

f 

CPU 

Fréquence de comptage donnée par : fTX 

= 

Txl 

4 ⋅ 2 

Exemple : Si Txl vaut 0 et f CPU = 20 MHz → f TX = 5 MHz (200 ns) 

Mode Compteur : 

Fonctionnement identique à T3. Voir page 37. 

Mode Commandé : 

Mode timer avec validation du comptage quand T6IN est actif (1 ou 0 selon le mode choisi). 

Bit 

T5I 

Function 

Timer 5 Input Selection 


T5M Timer 5 Mode Control (Basic Operating Mode) identique T6 

T5R Timer 5 Run Bit identique T6 

T5UD Timer 5 Up / Down Control identique T6 

T5UDE Timer 5 External Up/Down Enable identique T6 

CT3 

CI 

T5CLR 

T5SC 

Timer 3 Capture Trigger Enable 

0 : Capture trigger from pin CAPIN 

1 : Capture trigger from T3 input pins 

Register CAPREL Capture Trigger Selection (depending on bit CT3) 

00 : Capture disabled 

01 : Positive transition (rising edge) on CAPIN or any transition on T3IN 

10 : Negative transition (falling edge) on CAPIN or any transition on T3EUD 

11 : Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD 

Timer 5 Clear Bit 

0 : Timer 5 not cleared on a capture 

1 : Timer 5 is cleared on a capture 

Timer 5 Capture Mode Enable 

0 : Capture into register CAPREL disabled 

1 : Capture into register CAPREL enabled 

Modes Timer et Commandés : idem T6 

Mode Compteur : idem T2, avec sortie T6OTL (voir page 37) 

Mode Capture : T5 transféré dans CAPREL quand événement sur CAPIN ou sur entrée de T3. 

Mode Rechargement : CAPREL transféré dans T6 quand dépassement de T6 (passage de FFFFh à 0000h 

en comptage ou 0000h à FFFFh en décomptage). 

Registres d'interruption associés : T5IC, T6IC et CRIC (voir page 29).

Capture/Compare C167CR - 41 - 

Unités Capture/Compare 

• 2 unités CAPCOM 

• 32 voies, 4 timers (T0, T1, T7, T8) en comptage seulement (pas de décomptage) 

• Capture d'un timer à partir d'un événement interne ou externe 

• Déclenchement d'un événement lorsqu'un timer atteint une valeur prédéfinie 

• Résolution maximum : 8 cycles CPU 

• Horloge des timers avec prédiviseurs programmables, peut provenir de l'overflow de T6 

• T0 et T7 peuvent être mis en compteurs 

Chaque unité CAPCOM contient : 

- 2 timers 16 bits (T0/T1 pour CAPCOM1, T7/T8 pour CAPCOM2) 

- 2 registres de rechargement des timers (TxREL) 

- 1 banque de 16 registres de capture/comparaison 16 bits : 

CC0…CC15 pour CAPCOM1 (P2.0 … P2.15) 

CC16…CC31 pour CAPCOM2 (P8.0 … P8.7, P1H.4 … P1H.7, P7.4 … P7.7) 

T01CON et T78CON permettent de configurer les timers. 

Quand un timer effectue un overflow (FFFF H → 0000 H ), il est rechargé par TxREL. 

16 

Txl+ 

3 

( 2 − TxREL) 

⋅ 2 

La période correspondant est donnée par : PTX 

= 

f 

CPU


Bit 

TxI 

Function 

Timer/Counter x Input Selection 

Timer Mode (TxM = ‘0’): 

( + 3) 

Input Frequency = f CPU / 2 

Counter Mode (TxM = ‘1’): 

000 : Overflow/Underflow of GPT2 Timer 6 

001 : Positive (rising) edge on pin T7IN 1) 

010 : Negative (falling) edge on pin T7IN 1) 

011 : Any edge (rising and falling) on pin T7IN 1) 

1XX : Reserved 

TxM Timer/Counter x Mode Selection 

0 : Timer Mode (Input derived from internal clock) 

1 : Counter Mode (Input from External Input or T6) 

TxR Timer/Counter x Run Control 

0 : Timer/Counter x is disabled 

1 : Timer/Counter x is enabled 

1) This selection is available for timers T0 and T7. Timers T1 and T8 will stop at this selection! 

Les interruptions liées aux timers CAPCOM utilisent les registres T0IC, T1IC, T7IC et T8IC (voir 

page 29). 

Les registres de contrôle des unités CAPCOM sont CCM0 à CCM7 (8 registres 16 bits). 

Les CCMx contrôlent chacun 4 registres de capture/comparaison, permettant donc, au total de configurer 

les 32 modules de capture/comparaison.


CCMx (n = 4⋅x) : 

Bit 

ACCn 

Function 

Allocation Bit for Capture/Compare Register CCn 

0 : CCn allocated to Timer T0 (CAPCOM1) / Timer T7 (CAPCOM2) 

1 : CCn allocated to Timer T1 (CAPCOM1) / Timer T8 (CAPCOM2) 

CCMODn Selection for Capture/Compare Register CCn 

0 0 0 : Disable Capture and Compare Modes. The respective CAPCOM register may 

be used for general variable storage. 

0 0 1 : Capture on Positive Transition (Rising Edge) at Pin CCnIO 

0 1 0 : Capture on Negative Transition (Falling Edge) at Pin CCnIO 

0 1 1 : Capture on Positive and Negative Transition (Both Edges) at Pin CCnIO 

1 0 0 : Compare Mode 0: Interrupt Only. Several interrupts per timer period (CCx 

updated during the timer period); Enables double-register compare mode for registers 

CC8 … CC15 and CC24 … CC31 if the corresponding bank 1 register is programmed 

to compare mode 1. 

. 1 0 1 : Compare Mode 1: Toggle Output Pin on each Match. Several compare events 

per timer period; This mode is required for double - register compare mode for registers 

CC0 … CC7 and CC16 … CC23 if the corresponding bank 2 register is programmed to 

compare mode 0. 

1 1 0 : Compare Mode 2: Interrupt Only. Only one interrupt per timer period (After 

the first match, even when the compare register is reloaded with a value higher than the 

current timer value, no compare event will occur until the allocated timer overflows). 

1 1 1 : Compare Mode 3: Set Output Pin on each Match. When the first match within 

the timer period is detected the interrupt request flag CCxIR is set to ‘1’ and also the 

output pin CCxIO will be set to ‘1’. The pin will be reset to ‘0’, when the allocated 

timer overflows. Only one interrupt per timer period. 

Timing Example for Compare Modes 

0 and 1 : 

Timing Example for Compare Modes 

2 and 3 :

PWM C167CR - 44 - 

PWM 

Pulse Width Modulation 

• 4 signaux PWM indépendants (POUT0 à POUT3) 

• mode centré ou aligné sur fronts 

• résolution de 1 à 16 bits 

• fréquence de porteuse dépend de la résolution choisie 

Chaque PWM dispose de : 

- 1 compteur 16 bits (PTx) 

- 1 registre de période 16 bits (PPx) 

- 1 registre de largeur d'impulsion (PWx) 

- 2 comparateurs 

PWMCON0, PWMCON1 et PWMIC contrôlent les 4 PWM. 

Les sorties PWM sont combinées en OU exclusif avec les latches de sortie des ports P7.0 à P7.3 

→ inversion possible des sorties PWM 

Mode 0 : Mode aligné sur fronts 

PWM_Period = [PPx] + 1

PWM C167CR - 45 - 

Mode 1 : Mode centré 

PWM_Period = 2 ([PPx] + 1) 

Mode Burst 

ET logique entre PWM0 et PWM1 

→ sortie sur POUT0 

Utilisation des modes centrés ou alignés 

possibles. 

POUT1 utilisable. 

Mode "Single Shot" 

Sur PWM2 ou PWM3 

Impulsion unique retardée de t D . 

t D défini par PWx. 

Possibilité de modifier PTx pour modifier 

la largeur de l'impulsion

PWM C167CR - 46 - 

Registres associés aux modules PWM : 

Register Address (SFR) Register Address (ESFR) 

PW0 FE30H/18H PT0 F030H/18H 

PW1 FE32H/19H PT1 F032H/19H 

PW2 FE34H/1AH PT2 F034H/1AH 

PW3 FE36H/1BH PT3 F036H/1BH 

PP0 F038H/1CH 

PP1 F03AH/1DH 

PP2 F03CH/1EH 

PP3 F03EH/1FH 

Note: PWx, PTx & PPx are not bitaddressable 

Bit 

PTRx 

PTIx 

PIEx 

PIRx 

Function 

PWM Timer x Run Control Bit 

0 : Timer PTx is disconnected from its input clock 

1 : Timer PTx is running 

PWM Timer x Input Clock Selection 

0 : Timer PTx clocked with CLK CPU 

1 : Timer PTx clocked with CLK CPU /64 

PWM Channel x Interrupt Enable Flag 

0 : Interrupt from channel x disabled 

1 : Interrupt from channel x enabled 

PWM Channel x Interrupt Request Flag 

0 : No interrupt request from channel x 

1 : Channel x interrupt pending (must be reset via software) 

Bit 

PENx 

PMx 

PB01 

PSx 

Function 

PWM Channel x Output Enable Bit 

0 : Channel x output signal disabled, generate interrupt only 

1 : Channel x output signal enabled 

PWM Channel x Mode Control Bit 

0 : Channel x operates in mode 0, i.e. edge aligned PWM 

1 : Channel x operates in mode 1, i.e. center aligned PWM 

PWM Channel 0/1 Burst Mode Control Bit 

0 : Channel 0 and channel 1 work independently in their respective standard mode 

1 : Outputs of channels 0 and 1 are ANDed to POUT0 in burst mode 

PWM Channel x Single Shot Mode Control Bit 

0 : Channel x works in respective standard mode 

1 : Channel x operates in single shot mode

Convertisseur A/N C167CR - 47 - 

Convertisseur A/N 

• 16 entrées analogiques (Port 5) 

• 1 convertisseur 10 bits 

• Échantillonneur bloqueur intégré 

• Mode auto-scan 

Bit 

ADCH 

ADM 

ADST 

ADBSY 

ADWR 

ADCIN 

ADCRQ 

ADSTC 

Function 

ADC Analog Channel Input Selection 

Selects the (first) ADC channel which is to be converted. 

Note: Valid channel numbers are 0H to FH. 

ADC Mode Selection 

00 : Fixed Channel Single Conversion 

01 : Fixed Channel Continuous Conversion 

10 : Auto Scan Single Conversion 

11 : Auto Scan Continuous Conversion 

ADC Start Bit 

0 : Stop a running conversion 

1 : Start conversion(s) 

ADC Busy Flag 

0 : ADC is idle 

1 : A conversion is active. 

ADC Wait for Read Control 

Le résultat de conversion doit être lu pour permettre une nouvelle conversion. 

ADC Channel Injection Enable 

ADC Channel Injection Request Flag 

ADC Sample Time Control 

ADSTC 

8⋅ 2 

Defines the ADC sample time : tS 

= 

f 

ADCTC ADC Conversion Time Control (Defines the ADC basic conversion clock f BC ) 

00 : f BC = f CPU / 4 01 : f BC = f CPU / 2 

10 : f BC = f CPU / 16 11 : f BC = f CPU / 8 

BC

Convertisseur A/N C167CR - 48 - 

Conversion sur une voie : 

- mettre à 1 le bit ADST (doit être préalablement à 0) 

- ADBSY passe à 1 indiquant que la conversion est en cours 

- Quand la conversion est terminée, ADBSY passe à 0 et ADCIR passe à 1 

Mode conversion continue : 

- la conversion est relancée automatiquement sur le même canal. 

- ADCIR est mis à 1 à chaque fin de conversion 

- Mettre ADST à 0 pour arrêter les conversions (après la conversion en cours) 

Mode auto-scan : 

- Conversion d'une séquence de canaux depuis le canal spécifié jusqu'au canal 0 

- ADCIR passe à 1 à chaque fin de conversion 

- En mode conversion simple, ADBSY passe à 0 quand la séquence est terminée 

- En mode conversion continue, la mise à 0 de ADST arrête la séquence (après la conversion 

du canal 0) 

Mode injection de canal : 

- permet de convertir sur un canal pendant une conversion continue → insertion d'une 

conversion 

- autorisé par ADCIN=1 et ADWR=1 en mode continu 

- l'insertion est effectuée quand ADCRQ est mis à 1, ou par l'intermédiaire de CAPCOM2 

Interruptions associées : 

ADCIC 

ADC Conversion Intr.Ctrl.Reg. 

ADEIC 

ADC Error Intr.Ctrl.Reg. 

SFR (FF98H/CCH) 

SFR (FF9AH/CDH) 

Reset value: --00H 

Reset value: --00H

Port série C167CR - 49 - 

Port série

Interface CAN C167CR - 50 - 

Interface CAN 

Développé au milieu des années 80 par BOSCH 

Faible coût : 

• Bus série à 2 fils (1 paire torsadée) 

• Nombreux dispositifs faible coût disponibles dans l'automobile et pour l'industrie 

Fiabilité : 

• Détection d'erreur sophistiquée et gestion des erreurs (Exemple : 500kbit/s, charge bus 25%, 2000 

heures/an → 1 erreur détectée tous les mille ans) 

• Messages erronés détectés et répétés 

• Chaque nœud du bus est informé en cas d'erreur 

• Immunité élevée aux perturbations électromagnétiques 

Compatible temps réel : 

• Messages courts (0 à 8 octets de données par message) 

• Faible temps de latence entre la demande de transmission et le début réel de la transmission 

• Arbitrage intégré de la priorité des messages 

• Bus multi-maître : 

o Chaque nœud peut demander l'accès au bus 

o Les communications ne sont pas perturbées par un nœud défaillant 

o Les nœuds défaillants sont automatiquement déconnectés du bus 

Souplesse et rapidité : 

• Les nœuds peuvent être facilement connectés et déconnectés 

• Le nombre de nœuds n'est pas limité par le protocole 

• Débit maximum de 1 MBit/s (bus de 40 m) et environ 40 kBit/s (bus de 1000 m) 

Performance en communication : 

• Les messages peuvent s'adresser à un ou plusieurs nœuds 

• Tous les nœuds reçoivent simultanément les messages communs 

Bus standard : 

• Certifié par ISO-DIS 11898 (applications à haute vitesse) 

• Certifié par ISO-DIS 11519-2 (low speed applications à faible vitesse) 

Structure : 

• Bus série asynchrone de structure linéaire avec des nœuds identiques 

• L'adresse des nœuds est comprise dans le message, avec le niveau de priorité 

• 2 états : récessif (niveau 1) et dominant (niveau 0) 

• Chaque nœud est placé en parallèle sur le bus en ET câblé 

• Détection de collision avec arbitrage non destructif

Interface CAN C167CR - 51 - 

récessif 

Nœud A 

dominant 

Nœud B 

Bus CAN 

repos 

récessif 

dominant 

récessif 

dominant 

Le nœud B passe en récessif mais lit un état dominant 

→ le nœud B perd l'arbitrage du bus et passe en récepteur 

Un seul nœud est "parleur", les autres sont "écouteurs". 

Utilisation de trames : 

Identificateur Données (0 à 8 octets) CRC 

Tous les nœuds reçoivent les trames. Ceux qui ne sont pas concernés les ignorent. 

Lors d'une demande d'information, la trame (de commande) contient un identificateur et un CRC. 

L'identificateur contient l'information demandée et la priorité du message. Le nœud qui répond renvoie 

une trame (de données) contenant le même identificateur et les données demandées. 

Trame standard : 

- Identificateur sur 11 bits → CAN specification 2.0A 

Trames étendues : 

- Identificateur sur 29 bits (CAN specification 2.0B) 

Certains nœuds ne reconnaissent pas la spécif. 2.0B → ignorent les trames ou déclenchent une erreur. 

Certains contrôleurs ne trient pas les messages : les trames sont toutes archivées et doivent être examinées 

par le processeur → ok si bas débit ou peu de trames. 

Certains contrôleurs effectuent le tri des messages et ignorent les messages inutiles → moins de charge 

CPU. 

C167CR : 

- Compatible CAN 2.0B 

- Taux de transfert maximum : 

1 MBit/s 

- Gestion de 15 messages (en 

émission ou réception) permettant 

filtrage 

- Seul un transceiver est nécessaire 

pour la mise en œuvre.

PEC C167CR - 52 - 

Système PEC 

(Peripheral Event Controller) 

• 8 canaux permettant transfert automatique de données (octets ou mots) à l'intérieur du segment 0 

• Mis en œuvre en association avec interruptions 

• + rapide, - charge CPU que interruptions (programme interrompu pendant un seul cycle) 

Chaque canal est géré par les registres PECCx, SRCPx et DSTPx. 

Bit 

COUNT 

BWT 

INC 

Function 

PEC Transfer Count 

Counts PEC transfers and influences the channel’s action 

Byte/Word Transfer Selection 

0 : Transfer a Word 

1 : Transfer a Byte 

Increment Control (Modification of SRCPx or DSTPx) 

0 0 : Pointers are not modified 

0 1 : Increment DSTPx by 1 or 2 (BWT) 

1 0 : Increment SRCPx by 1 or 2 (BWT) 

1 1 : Reserved. Do not use this combination. (changed to ‘10’ by hardware) 

COUNT : 

Previous Modified IR after Action of PEC Channel and Comments 

COUNT COUNT PEC Service 

FFH FFH ‘0’ Move a Byte/Word 

Continuous transfer mode, i.e. COUNT is not modified 

FEH … 02H FDH … 01H ‘0’ Move a Byte/Word and decrement COUNT 

01H 00H ‘1’ Move a Byte/Word 

Leave request flag set, which triggers another request 

00H 00H (‘1’) No action! 

Activate interrupt service routine rather than PEC channel. 

→ quand COUNT atteint 0, l'interruption standard est déclenchée. 

PEC activée dans registre xxIC en mettant un niveau de priorité 14 ou 15 (avec count>0) 

Le groupe de priorité détermine le canal PEC à utiliser (priorité 14 : PEC 0 à 3, priorité 15 : PEC 4 à 7). 

Priority Level 

Type of Service 

ILVL GLVL COUNT = 00H COUNT ≠ 00H 

1 1 1 1 1 1 CPU interrupt, level 15, group priority 3 PEC service, channel 7 




1 1 0 1 1 0 CPU interrupt, level 13, group priority 2 CPU interrupt, level 13, group priority 2 



0 0 0 0 X X No service! No service!

Programmation C167CR - 53 - 

Programmation 

Instructions 

Mnemonics Addressing Modes Bytes Mnemonics Addressing Modes Bytes 

ADD[B] Rwn,Rwm 2 CPL[B] Rwn (Rbn) 1) 2 

ADDC[B] Rwn,[Rwi] 2 NEG[B] 

AND[B] Rwn,[Rwi+] 2 DIV Rwn 2 

DIVL 

OR[B] Rwn,#data3 2 DIVLU 

SUB[B] 

DIVU 

SUBC[B] reg,#data16 2) 4 MUL Rwn,Rwm 2 

XOR[B] 1) reg,mem 4 MULU 

mem,reg 4 CMPD1 Rwn,#data4 2 

ASHR Rwn,Rwm 2 CMPD2 

ROL Rwn,#data4 2 CMPI1 Rwn,#data16 4 

ROR CMPI2 Rwn,mem 4 

SHL CMP Rwn,Rwm 2 

SHR CMPB 1) Rwn,[Rwi] 2 

BAND bitaddrZ.z,bitaddrQ.q 4 Rwn,[Rwi+] 2 

BCMP Rwn,#data3 2 

BMOV reg,#data16 2) 4 

BMOVN reg,mem 4 

BOR CALLA cc,caddr 4 

BXOR 

JMPA 

BCLR bitaddrQ.q 2 CALLI cc,[Rwn] 2 

BSET 

JMPI 

BFLDH bitoffQ,#mask8, #data8 4 EXTP Rwm,#irang2 3) 2 

BFLDL EXTPR #pag,#irang2 4 

EXTS Rwm,#irang2 3) 2 SRST – 4 

EXTSR #seg,#irang2 4 IDLE 

NOP – 2 PWRDN 

RET 

SRVWDT 

RETI 

DISWDT 

RETS 

EINIT 

MOV Rwn,Rwm 2 CALLS seg,caddr 4 

MOVB 1) Rwn,#data4 2 JMPS 

Rwn,[Rwm] 2 CALLR rel 2 

Rwn,Rwm+] 2 JMPR cc,rel 2 

[Rwm],Rwn 2 JB bitaddrQ.q,rel 4 

[-Rwm],Rwn 2 JBC 

[Rwn],[Rwm] 2 JNB 

[Rwn+],[Rwm] 2 JNBS 

[Rwn],[Rwm+] 2 PCALL reg,caddr 4 

reg,#data16 2) 4 POP reg 2 

Rwn,[Rwm+#d16] 4 PUSH 

[Rwm+#d16],Rwn 4 RETP 

[Rwn],mem 4 SCXT reg,#data16 4 

mem,[Rwn] 4 reg,mem 4 

reg,mem 4 PRIOR Rwn,Rwm 2 

mem,reg 4 TRAP #trap7 2 

MOVBS Rwn,Rbm 2 ATOMIC #irang2 3) 2 

MOVBZ reg,mem 4 EXTR 

mem,reg 4 

1) Byte oriented instructions (suffix ‘B’) use byte registers (Rb instead of Rw), except for indirect modes 

([Rw] or [Rw+]). 

2) Byte oriented instructions (suffix ‘B’) use #data8 instead of #data16. 

3) The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.


MOV : Move Data 

Syntax MOV op1, op2 

(op1) ← (op2) 

SUB : Integer Subtraction 

Syntax SUB op1, op2 

(op1) ← (op1) - (op2) 

BFLDH : Bit Field High Byte 

Syntax BFLDH op1, op2, op3 

(tmp) ← (op1) 

(high byte (tmp)) ← ((high byte (tmp) & ~op2) | op3) 

(op1) ← (tmp) 

BMOVN : Bit to Bit Move and Negate 

Syntax BMOVN op1, op2 

(op1) ← ~(op2) 

CMPD1 : Integer Compare and Decrement by 1 

Syntax CMPD1 op1, op2 

(op1) ⇔ (op2) 

(op1) ← (op1) - 1 

CMPD2 : Integer Compare and Decrement by 2 

CMPI1 : Integer Compare and Increment by 1 

DIV : 16-by-16 Signed Division 

Syntax DIV op1 

MDRIU = 1 

(MDL) ← (MDL) / (op1) 

(MDH) ← (MDL) % (op1) 

MOVBS : Move Byte Sign Extend 

MOVBZ : Move Byte Zero Extend 

CALLA : Call Subroutine Absolute 

Syntax CALLA op1, op2 

IF (op1) THEN 

(SP) ← (SP) – 2 

((SP)) ← (IP) 

(IP) ← op2 

ELSE 

next instruction 

END IF 

CALLI : Call Subroutine Indirect 

CALLR: Call Subroutine Relative 

CALLS : Call Inter-Segment Subroutine A branch is taken to the absolute location specified by op2 

within the segment specified by op1. [→ RETS] 

PCALL : Push Word and Call Subroutine Absolute [→ RETP] 

Syntax PCALL op1, op2 

(tmp) ← (op1) 

(SP) ← (SP) - 2 

((SP)) ← (tmp) 

(SP) ← (SP) - 2


((SP)) ← (IP) 

(IP) ← op2 

JB : Relative Jump if Bit Set 

Syntax JB op1, op2 

IF (op1) = 1 THEN 

(IP) ← (IP) + sign_extend (op2) 

ELSE 

Next Instruction 

END IF 

JBC : Relative Jump if Bit Set and Clear Bit 

Syntax JBC op1, op2 

IF (op1) = 1 THEN 

(op1) = 0 

(IP) ← (IP) + sign_extend (op2) 

ELSE 


END IF 

TRAP : Software Trap → TRAP #trap7 

SCXT : Switch Context 

Syntax SCXT op1, op2 

(tmp1) ← (op1) 

(tmp2) ← (op2) 

(SP) ← (SP) - 2 

((SP)) ← (tmp1) 

(op1) ← (tmp2) 

Used to switch contexts for any register. Switching 

context is a push and load operation. The contents of the 

register specified by the first operand, op1, are pushed 

onto the stack. That register is then loaded with the 

value specified by the second operand, op2. 

PRIOR : Prioritize Register 

Syntax PRIOR op1, op2 

(tmp) ← (op2) 

(count) ← 0 

DO WHILE (tmp15) ≠ 1 AND (count) ≠ 15 AND (op2) ≠ 0 

(tmpn) ← (tmpn-1) 

(count) ← (count) + 1 

END WHILE 

(op1) ← (count) 

EXTR : Begin EXTended Register Sequence 

Syntax EXTR op1 

(count) ← (op1) [1 ≤ op1 ≤ 4] 

Disable interrupts and Class A traps 

SFR_range = Extended 

DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) 


(count) ← (count) - 1 

END WHILE 

(count) = 0 

SFR_range = Standard 

Enable interrupts and traps


EXTP : Begin EXTended Page Sequence 

Syntax EXTP op1, op2 

(count) ← (op2) [1 ≤ op2 ≤ 4] 


Data_Page = (op1) 




END WHILE 

(count) = 0 

Data_Page = (DPPx) 

Enable interrupts and traps 

EXTPR : Begin EXTended Page and Register Sequence 

Syntax EXTPR op1, op2 

(count) ← (op2) [1 ≤ op2 ≤ 4] 


Data_Page = (op1) AND SFR_range = Extended 




END WHILE 

(count) = 0 

Data_Page = (DPPx) AND SFR_range = Standard 


EXTS : Begin EXTended Segment Sequence 

Syntax EXTS op1, op2 

(count) ← (op2) [1 ≤ op2 ≤ 4] 


Data_Segment = (op1) 




END WHILE 

(count) = 0 

Data_Page = (DPPx) 


EXTSR : Begin EXTended Segment and Register Sequence 

Syntax EXTSR op1, op2 

(count) ← (op2) [1 ≤ op2 ≤ 4] 


Data_Segment = (op1) AND SFR_range = Extended 




END WHILE 

(count) = 0 

Data_Page = (DPPx) AND SFR_range = Standard 

Enable interrupts and traps


ATOMIC : Begin ATOMIC Sequence 

Syntax ATOMIC op1 

Operation (count) ← (op1) [1 ≤ op1 ≤ 4] 




(count) ← (count) – 1 

END WHILE 

(count) = 0 


DISWDT : Disable Watchdog Timer 

SRVWDT : Service Watchdog Timer 

EINIT : End of Initialization. This instruction is used to signal the end of the initialization portion of a 

program. After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT 

instruction has been executed at which time it goes high. This enables the program to signal the 

external circuitry that it has successfully initialized the microcontroller. After the EINIT instruction 

has been executed, execution of the Disable Watchdog Timer instruction (DISWDT) has no effect. 

SRST : Software Reset 

IDLE : Enter Idle Mode 

PWRDN : Enter Power Down Mode 

ConditionCode (cc) Test Description 

cc_UC 1 = 1 Unconditional 

cc_Z Z = 1 Zero 

cc_NZ Z = 0 Not zero 

cc_V V = 1 Overflow 

cc_NV V = 0 No overflow 

cc_N N = 1 Negative 

cc_NN N = 0 Not negative 

cc_C C = 1 Carry 

cc_NC C = 0 No carry 

cc_EQ Z = 1 Equal 

cc_NE Z = 0 Not equal 

cc_ULT C = 1 Unsigned less than 

cc_ULE (Z+C) = 1 Unsigned less than or equal 

cc_UGE C = 0 Unsigned greater than or equal 

cc_UGT (Z+C) = 0 Unsigned greater than 

cc_SLT (N⊕V) = 1 Signed less than 

cc_SLE (Z+(N⊕V)) = 1 Signed less than or equal 

cc_SGE (N⊕V) = 0 Signed greater than or equal 

cc_SGT (Z+(N⊕V)) = 0 Signed greater than 

cc_NET (Z+E) = 0 Not equal AND not end of table


Adressages 

→ Accès aux mots, aux octets ou aux bits (en adressage long, court ou indirect) 

→ accès à une adresse d'un branchement (absolu, relatif ou indirect) 

Plan mémoire de 16 Mo ⇒ 24 lignes d'adresses. 

Adressage court : 

Permet d'utiliser une adresse de base + offset 8 bits. 

→ accès aux GPRs, SFRs, ESFRs et mémoire bit-adressable. 

Mnemonic Physical Address Short Address Range Scope of Access 

Rw (CP) + 2 x Rw Rw = 0 … 15 GPRs (word) 

Rb (CP) + 1 x Rb Rb = 0 … 15 GPRs (byte) 

reg 00’FE00H + 2 x reg Reg = 00H … EFH SFRs (word, low byte) 

00’F000H + 2 x reg Reg = 00H … EFH ESFRs (word, low byte) 

(CP) + 2 x (reg&0FH) Reg = F0H … FFH GPRs (word) 

(CP) + 1 x (reg&0FH) Reg = F0H … FFH GPRs (byte) 

bitoff 00’FD00H + 2 x bitoff Bitoff = 00H … 7FH RAM bit word offset 

00’FF00H + 2 x (bitoff&7FH) Bitoff = 80H … EFH SFR bit word offset 

00’F100H + 2 x (bitoff&7FH) Bitoff = 80H … EFH ESFR bit word offset 

(CP) + 2 x (bitoff&0FH) Bitoff = F0H … FFH GPR bit word offset 

bitaddr Word offset as with bitoff. Bitoff = 00H … FFH 

Immediate bit position. Bitpos = 0 … 15 

Any single bit 

Adressage long : 

Permet d'accéder à l'ensemble de la mémoire. 

Adressage indirect : 

Mnemonic 

[Rw] 

Particularities 

Most instructions accept any GPR (R15 … R0) as indirect address pointer. 

Some instructions, however, only accept the lower four GPRs (R3 … R0). 

[Rw+] The specified indirect address pointer is automatically post-incremented by 2 or 1 

(for word or byte data operations) after the access. 

[-Rw] The specified indirect address pointer is automatically pre-decremented by 2 or 1 

(for word or byte data operations) before the access. 

[Rw+ #data16] 

The specified 16-bit constant is added to the indirect address pointer, before the 

long address is calculated.


Constantes : 

→ adressage immédiat. Constantes de 3, 4, 8 ou 16 bits. 

→ précédées de '#'. 

Adressages des branchements : 

Mnemonic Target Address Target Segment Valid Address Range 

caddr (IP) = caddr -current- Caddr = 0000H … FFFEH 

rel (IP) = (IP) + 2 x rel -current- Rel = 00H … 7FH 

(IP) = (IP) - 2 x (~rel+1) -current- Rel = 80H … FFH 

[Rw] (IP) = ((CP) + 2 x Rw) -current- Rw = 0 … 15 

seg – (CSP) = seg Seg = 0 … 255(3) 

#trap7 (IP) = 0000H + 4 x trap7 (CSP) = 0000H trap7 = 00H … 7FH

Bus externe C167CR - 60 - 

Bus externe 

Le mode microcontrôleur (Single Chip) est obtenu lorsque EA# est à 1 pendant RESET. 

→ accès au bus externe impossible 

Le bus externe permet d'accéder à l'espace d'adressage de 16 Mo. 

Contrôlé par EBC (External Bus Contoller) et registres SYSCON, BUSCONx, ADDRSELx. 

Utilise des lignes de P0, P1, P3, P4 et P6. 

4 modes possibles : 

bus multiplexé ou non, bus de données 8 ou 16 bits 

bus multiplexé 

bus démultiplexé


Les lignes EA, ALE#, READY#, WR#/WRL# et RD# sont physiquement présentent sur le C167. Les 

autres lignes permettant l'accès au bus sont multiplexées avec les ports d'entrées/sorties. 

Utilisation des Ports : 

• P4 : Lignes d'adresses A23 à A16 (possibilité de limiter l'espace d'adressage à 64 Ko, 256 Ko ou 

1Mo, afin d'utiliser moins de lignes de P4. 

• P6.0:4 : lignes de décodage (0, 2, 3 ou 5 : CS0# à CS4#) 

P6.5 : HOLD# (entrée, demande accès au bus) 

P6.6 : HLDA# (sortie, indique bus libéré quand un autre processeur a demandé le bus du C167), 

ou BGR# (entrée, lorsque le C167 a demandé l'accès à un bus "étranger" ; indique que le bus est 

accordé). 

P6.7 : BREQ# (sortie, indique que le C167 veut reprendre le contrôle du bus externe) 

• P3.12 : BHE# ou WRH# 

Exemples de partage de bus : 

Utilisation des ports P0 et P1 et facteur de rapidité en fonction des modes : 

Mode Ports Rapidité (byte / word / dword) 

Données 16 bits – bus multiplexé P0L, P0H : Adresses, données 1,5 / 1,5 / 3 

Données 16 bits – bus non multiplexé P1L, P1H : Adresses 1 / 1 / 2 

P0L, P0H : Données 

Données 8 bits – bus multiplexé P0L, P0H : Adresses 1,5 / 3 / 6 

P0L : Données 

Données 8 bits – bus non multiplexé P1L, P1H : Adresses 

P0L : Données 

1 / 2 / 4


Registres associés à l'EBC 

Bit 

XPER- 

SHARE 

VISIBLE 

XPEN 

BDRSTEN 

OWDDIS 

CSCFG 

WRCFG 

CLKEN 

BYTDIS 

ROMEN 

SGTDIS 

ROMS1 

Function 

XBUS Peripheral Share Mode Control 

0: External accesses to XBUS peripherals are disabled 

1: XBUS peripherals are accessible via the ext. bus during hold mode 

Visible Mode Control 

0: Accesses to XBUS peripherals are done internally 

1: XBUS peripheral accesses are made visible on the external pins 

XBUS Peripheral Enable Bit 

0: Accesses to the on-chip X-Peripherals and their functions are disabled 

1: The on-chip X-Peripherals are enabled and can be accessed 

Bidirectional Reset Enable Bit 

0: Pin RSTIN is an input only. 

1: Pin RSTIN is pulled low during the internal reset sequence after any reset. 

Oscillator Watchdog Disable Bit (Cleared after reset) 

0: The on-chip oscillator watchdog is enabled and active. 

1: The on-chip oscillator watchdog is disabled and the CPU clock is always fed from the 

oscillator input. 

Chip Select Configuration Control (Cleared after reset) 

0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins 

synchronously. 

1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the 

(enabled) port pins. 

Write Configuration Control (Set according to pin P0H.0 during reset) 

0: Pins WR and BHE retain their normal function 

1: Pin WR acts as WRL, pin BHE acts as WRH 

System Clock Output Enable (CLKOUT, cleared after reset) 

0: CLKOUT disabled: pin may be used for general purpose IO 

1: CLKOUT enabled: pin outputs the system clock signal 

Disable/Enable Control for Pin BHE (Set according to data bus width) 

0: Pin BHE enabled 

1: Pin BHE disabled, pin may be used for general purpose IO 

Internal ROM Enable (Set according to pin EA during reset) 

0: Internal program memory disabled, accesses to the ROM area use the external bus 

1: Internal program memory enabled 

Segmentation Disable/Enable Control (Cleared after reset) 

0: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) 

1: Segmentation disabled (Only IP is saved/restored) 

Internal ROM Mapping 



STKSZ System Stack Size 

Selects the size of the system stack (in the internal RAM) from 32 to 512 words 

Note: Register SYSCON cannot be changed after execution of the EINIT instruction. 

Bit SGTDIS controls the correct stack operation (push/pop of CSP or not) during traps and interrupts.


BUSCONx 

SFR Reset value 

BUSCON0 Bus Control Register 0 (FF0CH/86H) 0XX0H 

BUSCON1 Bus Control Register 1 (FF14H/8AH) 0000H 

BUSCON2 Bus Control Register 2 (FF16H/8BH) 0000H 

BUSCON3 Bus Control Register 3 (FF18H/8CH) 0000H 

BUSCON4 Bus Control Register 4 (FF1AH/8DH) 0000H 

Note: BUSCON0 is initialized with 00C0H, if pin EA is high during reset. If pin EA is low during reset, 

bits BUSACT0 and ALECTL0 are set (‘1’) and bit field BTYP is loaded with the bus configuration 

selected via PORT0. 

Bit 

MCTC 

RWDCx 

MTTCx 

BTYP 

ALECTLx 

BUSACTx 

RDYENx 

CSRENx 

CSWENx 

Function 

Memory Cycle Time Control (Number of memory cycle time wait states) 

0000: 15 waitstates 

… (Number = 15 – ) 

1111: No waitstates 

Note: The definition of bitfield MCTCx changes if RDYENx = ‘1’ 

Read/Write Delay Control for BUSCONx 

0: With rd/wr delay: activate command 1 TCL after falling edge of ALE 

1: No rd/wr delay: activate command with falling edge of ALE 

Memory Tristate Time Control 

0: 1 waitstate 

1: No waitstate 

External Bus Configuration 

00: 8-bit Demultiplexed Bus 

01: 8-bit Multiplexed Bus 

10: 16-bit Demultiplexed Bus 

11: 16-bit Multiplexed Bus 

Note: For BUSCON0 BTYP is defined via PORT0 during reset. 

ALE Lengthening Control 

0: Normal ALE signal 

1: Lengthened ALE signal 

Bus Active Control 

0: External bus disabled 

1: External bus enabled within respective address window (ADDRSEL) 

READY Input Enable 

0: External bus cycle is controlled by bit field MCTC only 

1: External bus cycle is controlled by the READY input signal 

Read Chip Select Enable 

0: The CS signal is independent of the read command (RD) 

1: The CS signal is generated for the duration of the read command 

Write Chip Select Enable 

0: The CS signal is independent of the write cmd. (WR,WRL,WRH) 

1: The CS signal is generated for the duration of the write command


ADDRSELx 

SFR Reset value 

ADDRSEL1 Address Select Register 1 (FF18H/0CH) 0000H 

ADDRSEL2 Address Select Register 2 (FE1AH/0DH) 0000H 

ADDRSEL3 Address Select Register 3 (FE1CH/0EH) 0000H 

ADDRSEL4 Address Select Register 4 (FE1EH/0FH) 0000H 

Bit 

RGSZ 

RGSAD 

Function 

Range Size Selection 

Defines the size of the address area controlled by the respective BUSCONx/ADDRSELx 

register pair. 

RGSZ=0…11 : Size = 4Kb . 2 RGSZ 

RGSZ=12…15 : reserved 

Range Start Address 

Defines the upper bits of the start address of the respective address area. 

Bit 

WRC 

CSSEL 

SALSEL 

CLKCFG 

Function 

Write Configuration 

0: Pins WR and BHE operate as WRL and WRH signals 

1: Pins WR and BHE operate as WR and BHE signals 

Chip Select Line Selection (Number of active CS outputs) 

00: 3 CS lines: CS2 …CS0 

01: 2 CS lines: CS1 … CS0 

10: No CS lines at all 

11: 5 CS lines: CS4 …CS0 (Default without pulldowns) 

Segment Address Line Selection (nr. of active segment addr. outputs) 

00: 4-bit segment address: A19 … A16 

01: No segment address lines at all 

10: 8-bit segment address: A23 … A16 

11: 2-bit segment address: A17 … A16 (Default without pulldowns) 

Clock Generation Mode Configuration 

These pins define the clock generation mode, i.e. the mechanism how the internal 

CPU clock is generated from the externally applied (XTAL) input clock. 

Note: RP0H cannot be changed via software, but rather allows to check the current configuration.

Registres C167CR - 65 - 

Liste des registres 

Name 

Physical 

Address 

8-bit 

Addr. 

Description 

Reset 

Value 

ADCIC b FF98H CCH A/D Converter End of Conversion Interrupt Control Register 0000H 

ADCON b FFA0H D0H A/D Converter Control Register 0000H 

ADDAT FEA0H 50H A/D Converter Result Register 0000H 

ADDAT2 F0A0H E 50H A/D Converter 2 Result Register 0000H 

ADDRSEL1 FE18H 0CH Address Select Register 1 0000H 

ADDRSEL2 FE1AH 0DH Address Select Register 2 0000H 

ADDRSEL3 FE1CH 0EH Address Select Register 3 0000H 

ADDRSEL4 FE1EH 0FH Address Select Register 4 0000H 

ADEIC b FF9AH CDH A/D Converter Overrun Error Interrupt Control Register 0000H 

BUSCON0 b FF0CH 86H Bus Configuration Register 0 0000H 

BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000H 

BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000H 

BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000H 

BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000H 

C1BTR EF04H X – CAN1 Bit Timing Register UUUUH 

C1CSR EF00H X – CAN1 Control/Status Register XX01H 

C1GMS EF06H X – CAN1 Global Mask Short UFUUH 

C1IR EF02H X – CAN1 Interrupt Register XXH 

C1LARn EFn4H X – CAN1 Lower Arbitration Register (msg. n) UUUUH 

C1LGML EF0AH X – CAN1 Lower Global Mask Long UUUUH 

C1LMLM EF0EH X – CAN1 Lower Mask of Last Message UUUUH 

C1MCFGn EFn6H X – CAN1 Message Configuration Register (msg. n) UUH 

C1MCRn EFn0H X – CAN1 Message Ctrl. Reg. (msg. n) UUUUH 

C1UARn EFn2H X – CAN1 Upper Arbitration Reg. (msg. n) UUUUH 

C1UGML EF08H X – CAN1 Upper Global Mask Long UUUUH 

C1UMLM EF0CH X – CAN1 Upper Mask of Last Message UUUUH 

CAPREL FE4AH 25H GPT2 Capture/Reload Register 0000H 

CC0 FE80H 40H CAPCOM Register 0 0000H 

CC0IC b FF78H BCH CAPCOM Register 0 Interrupt Ctrl. Reg. 0000H 


CC10 FE94H 4AH CAPCOM Register 10 0000H 

CC10IC b FF8CH C6H CAPCOM Register 10 Interrupt Ctrl. Reg. 0000H 

CC11 FE96H 4BH CAPCOM Register 11 0000H 

CC11IC b FF8EH C7H CAPCOM Register 11 Interrupt Ctrl. Reg. 0000H 

CC12 FE98H 4CH CAPCOM Register 12 0000H 

CC12IC b FF90H C8H CAPCOM Register 12 Interrupt Ctrl. Reg. 0000H 

CC13 FE9AH 4DH CAPCOM Register 13 0000H 


CC14 FE9CH 4EH CAPCOM Register 14 0000H 

CC14IC b FF94H CAH CAPCOM Register 14 Interrupt Ctrl. Reg. 0000H 

CC15 FE9EH 4FH CAPCOM Register 15 0000H 

CC15IC b FF96H CBH CAPCOM Register 15 Interrupt Ctrl. Reg. 0000H 


CC16IC b F160H E B0H CAPCOM Register 16 Interrupt Ctrl. Reg. 0000H 







CC1IC b FF7AH BDH CAPCOM Register 1 Interrupt Ctrl. Reg. 0000H 




CC21 FE6AH 35H CAPCOM Register 21 0000H 

CC21IC b F16AH E B5H CAPCOM Register 21 Interrupt Ctrl. Reg. 0000H 

CC22 FE6CH 36H CAPCOM Register 22 0000H


CC22IC b F16CH E B6H CAPCOM Register 22 Interrupt Ctrl. Reg. 0000H 

CC23 FE6EH 37H CAPCOM Register 23 0000H 

CC23IC b F16EH E B7H CAPCOM Register 23 Interrupt Ctrl. Reg. 0000H 





CC26 FE74H 3AH CAPCOM Register 26 0000H 

CC26IC b F174H E BAH CAPCOM Register 26 Interrupt Ctrl. Reg. 0000H 

CC27 FE76H 3BH CAPCOM Register 27 0000H 

CC27IC b F176H E BBH CAPCOM Register 27 Interrupt Ctrl. Reg. 0000H 

CC28 FE78H 3CH CAPCOM Register 28 0000H 

CC28IC b F178H E BCH CAPCOM Register 28 Interrupt Ctrl. Reg. 0000H 

CC29 FE7AH 3DH CAPCOM Register 29 0000H 

CC29IC b F184H E C2H CAPCOM Register 29 Interrupt Ctrl. Reg. 0000H 

CC2IC b FF7CH BEH CAPCOM Register 2 Interrupt Ctrl. Reg. 0000H 


CC30 FE7CH 3EH CAPCOM Register 30 0000H 

CC30IC b F18CH E C6H CAPCOM Register 30 Interrupt Ctrl. Reg. 0000H 

CC31 FE7EH 3FH CAPCOM Register 31 0000H 

CC31IC b F194H E CAH CAPCOM Register 31 Interrupt Ctrl. Reg. 0000H 

CC3IC b FF7EH BFH CAPCOM Register 3 Interrupt Ctrl. Reg. 0000H 



CC5 FE8AH 45H CAPCOM Register 5 0000H 


CC6 FE8CH 46H CAPCOM Register 6 0000H 


CC7 FE8EH 47H CAPCOM Register 7 0000H 





CC9IC b FF8AH C5H CAPCOM Register 9 Interrupt Ctrl. Reg. 0000H 

CCM0 b FF52H A9H CAPCOM Mode Control Register 0 0000H 

CCM1 b FF54H AAH CAPCOM Mode Control Register 1 0000H 

CCM2 b FF56H ABH CAPCOM Mode Control Register 2 0000H 

CCM3 b FF58H ACH CAPCOM Mode Control Register 3 0000H 

CCM4 b FF22H 91H CAPCOM Mode Control Register 4 0000H 




CP FE10H 08H CPU Context Pointer Register FC00H 

CRIC b FF6AH B5H GPT2 CAPREL Interrupt Control Register 0000H 

CSP FE08H 04H CPU Code Segment Pointer Register(8 bits, not directly writeable) 0000H 

DP0H b F102H E 81H P0H Direction Control Register 00H 

DP0L b F100H E 80H P0L Direction Control Register 00H 

DP1H b F106H E 83H P1H Direction Control Register 00H 

DP1L b F104H E 82H P1L Direction Control Register 00H 

DP2 b FFC2H E1H Port 2 Direction Control Register 0000H 

DP3 b FFC6H E3H Port 3 Direction Control Register 0000H 

DP4 b FFCAH E5H Port 4 Direction Control Register 00H 

DP6 b FFCEH E7H Port 6 Direction Control Register 00H 

DP7 b FFD2H E9H Port 7 Direction Control Register 00H 

DP8 b FFD6H EBH Port 8 Direction Control Register 00H 

DPP0 FE00H 00H CPU Data Page Pointer 0 Register (10 bits) 0000H 




EXICON b F1C0H E E0H External Interrupt Control Register 0000H 

MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H 

MDH FE0CH 06H CPU Multiply Divide Register – High Word 0000H 

MDL FE0EH 07H CPU Multiply Divide Register – Low Word 0000H


ODP2 b F1C2H E E1H Port 2 Open Drain Control Register 0000H 

ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000H 

ODP6 b F1CEH E E7H Port 6 Open Drain Control Register 00H 

ODP7 b F1D2H E E9H Port 7 Open Drain Control Register 00H 

ODP8 b F1D6H E EBH Port 8 Open Drain Control Register 00H 

ONES b FF1EH 8FH Constant Value 1’s Register (read only) FFFFH 

P0H b FF02H 81H Port 0 High Register (Upper half of PORT0) 00H 

P0L b FF00H 80H Port 0 Low Register (Lower half of PORT0) 00H 

P1H b FF06H 83H Port 1 High Register (Upper half of PORT1) 00H 

P1L b FF04H 82H Port 1 Low Register (Lower half of PORT1) 00H 

P2 b FFC0H E0H Port 2 Register 0000H 

P3 b FFC4H E2H Port 3 Register 0000H 

P4 b FFC8H E4H Port 4 Register (7 bits) 00H 

P5 b FFA2H D1H Port 5 Register (read only) XXXXH 

P5DIDIS b FFA4H D2H Port 5 Digital Input Disable Register 0000H 

P6 b FFCCH E6H Port 6 Register (8 bits) 00H 

P7 b FFD0H E8H Port 7 Register (8 bits) 00H 

P8 b FFD4H EAH Port 8 Register (8 bits) 00H 

PDCR F0AAH E 55H Port Driver Control Register 0000H 

PECC0 FEC0H 60H PEC Channel 0 Control Register 0000H 





PECC5 FECAH 65H PEC Channel 5 Control Register 0000H 

PECC6 FECCH 66H PEC Channel 6 Control Register 0000H 

PECC7 FECEH 67H PEC Channel 7 Control Register 0000H 

PICON F1C4H E E2H Port Input Threshold Control Register 0000H 

PP0 F038H E 1CH PWM Module Period Register 0 0000H 

PP1 F03AH E 1DH PWM Module Period Register 1 0000H 

PP2 F03CH E 1EH PWM Module Period Register 2 0000H 

PP3 F03EH E 1FH PWM Module Period Register 3 0000H 

PSW b FF10H 88H CPU Program Status Word 0000H 

PT0 F030H E 18H PWM Module Up/Down Counter 0 0000H 

PT1 F032H E 19H PWM Module Up/Down Counter 1 0000H 

PT2 F034H E 1AH PWM Module Up/Down Counter 2 0000H 

PT3 F036H E 1BH PWM Module Up/Down Counter 3 0000H 

PW0 FE30H 18H PWM Module Pulse Width Register 0 0000H 

PW1 FE32H 19H PWM Module Pulse Width Register 1 0000H 

PW2 FE34H 1AH PWM Module Pulse Width Register 2 0000H 

PW3 FE36H 1BH PWM Module Pulse Width Register 3 0000H 

PWMCON0 b FF30H 98H PWM Module Control Register 0 0000H 

PWMCON1 b FF32H 99H PWM Module Control Register 1 0000H 

PWMIC b F17EH E BFH PWM Module Interrupt Control Register 0000H 

RP0H b F108H E 84H System Startup Configuration Register(read only) XXH 

S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H 

S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H 

S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H 

S0RBUF FEB2H 59H Serial Channel 0 Receive Buffer Register(read only) XXXXH 

S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt Control Register 0000H 

S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H 

S0TBUF FEB0H 58H Serial Channel 0 Transmit Buffer Register 0000H 

S0TIC b FF6CH B6H Serial Channel 0 Transmit Interrupt Control Register 0000H 

SP FE12H 09H CPU System Stack Pointer Register FC00H 

SSCBR F0B4H E 5AH SSC Baudrate Register 0000H 

SSCCON b FFB2H D9H SSC Control Register 0000H 

SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000H 

SSCRB F0B2H E 59H SSC Receive Buffer XXXXH 

SSCRIC b FF74H BAH SSC Receive Interrupt Control Register 0000H 

SSCTB F0B0H E 58H SSC Transmit Buffer 0000H 

SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000H 

STKOV FE14H 0AH CPU Stack Overflow Pointer Register FA00H 

STKUN FE16H 0BH CPU Stack Underflow Pointer Register FC00H


SYSCON b FF12H 89H CPU System Configuration Register 0xx0H 1) 

T0 FE50H 28H CAPCOM Timer 0 Register 0000H 

T01CON b FF50H A8H CAPCOM Timer 0 and Timer 1 Ctrl. Reg. 0000H 

T0IC b FF9CH CEH CAPCOM Timer 0 Interrupt Ctrl. Reg. 0000H 

T0REL FE54H 2AH CAPCOM Timer 0 Reload Register 0000H 

T1 FE52H 29H CAPCOM Timer 1 Register 0000H 

T1IC b FF9EH CFH CAPCOM Timer 1 Interrupt Ctrl. Reg. 0000H 

T1REL FE56H 2BH CAPCOM Timer 1 Reload Register 0000H 

T2 FE40H 20H GPT1 Timer 2 Register 0000H 

T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H 

T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H 













T7 F050H E 28H CAPCOM Timer 7 Register 0000H 

T78CON b FF20H 90H CAPCOM Timer 7 and 8 Control Register 0000H 

T7IC b F17AH E BDH CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000H 

T7REL F054H E 2AH CAPCOM Timer 7 Reload Register 0000H 

T8 F052H E 29H CAPCOM Timer 8 Register 0000H 

T8IC b F17CH E BEH CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000H 

T8REL F056H E 2BH CAPCOM Timer 8 Reload Register 0000H 

TFR b FFACH D6H Trap Flag Register 0000H 

WDT FEAEH 57H Watchdog Timer Register (read only) 0000H 

WDTCON b FFAEH D7H Watchdog Timer Control Register 00xxH 2) 

XP0IC b F186H E C3H CAN1 Interrupt Control Register 0000H 

XP1IC b F18EH E C7H Unassigned Interrupt Control Register 0000H 

XP2IC b F196H E CBH Unassigned Interrupt Control Register 0000H 

XP3IC b F19EH E CFH PLL/OWD Interrupt Control Register 0000H 

ZEROS b FF1CH 8EH Constant Value 0’s Register (read only) 0000H 

1) The system configuration is selected during reset. 

2) The reset value depends on the indicated reset source. 

Bit-addressable SFRs are marked with the letter “b”. 

SFRs within the extended SFR-space (ESFRs) are marked with the letter “E”. 

Registers within on-chip X-Peripherals are marked with the letter “X”.

Compilateur C C167CR - 69 - 

Compilateur Tasking C166 

Types de données 

→ types standard + bit, sfr, sfrbit, bitword, pointeurs courts ou longs 

Taille des données 

Data Type Size (bytes) Range 

_bit 1 bit 0 or 1 

_sfrbit 1 bit 0 or 1 

_esfrbit 1 bit 0 or 1 

signed char 1 -128 to +127 

unsigned char 1 0 to 255U 

_sfr 2 0 to 65535U 

_esfr 2 0 to 65535U 

_xsfr 2 0 to 65535U 

signed short 2 -32768 to +32767 

unsigned short 2 0 to 65535U 

_bitword 2 0 to 65535U 

signed int 2 -32768 to +32767 

unsigned int 2 0 to 65535U 

signed long 4 -2147483648 to +2147483647 

unsigned long 4 0 to 4294967295UL 

float 4 +/- 1,176E-38 to +/- 3,402E+38 

double 8 +/- 2,225E-308 to +/- 1,797E+308 

long double 8 +/- 2,225E-308 to +/- 1,797E+308 

_near pointer 2 16 bits (64K) when using -Mt/-Ms 

14 bits (16K) when using -Mm/-Ml 

(default data group) 

_xnear pointer 2 14 bits (16K) when using -Mm/-Ml. 

Not allowed in non-segmented memory models. 

_far pointer 4 14 bits (16K) in any page (16M) 

_huge pointer 4 24 bits (16M) 

_shuge pointer 4 24 bits (16M), but arithmetic is done 16-bit wide 

Implémentation et extensions 

Fichier de définition des registres 

#include 

Modèles de mémoire 

Model 

DPP 

usage 

$SEGMENTED 

control 

CPU 

segmented 

mode 

normal 

data size 

code size 

far/huge/ 

shuge data 

allowed 

near data 

allowed 

tiny linear no no 64K yes yes


_bita 

Utilisation de bits dans des entiers ou des structures en RAM bit-adressable 

→ optimisation du code 

Exemples : 

_bita struct { 

unsigned bf1:1; 

unsigned pit:2; 

unsigned bf2:1; 

} s; 

_bita int w; 

_at(adresse) 

→ Indique l'adresse d'une variable globale. 

Exemples : 

_near int i _at(0x29000); 

_far const char ch _at(0x2A900) = 100; 

int j, * k _at(0x2B002); 

int * (* * fptr)(int, int) _at(0x12344); 

_atbit( name, offset ) 

→ définition de bits dans sfrs ou bitwords (uiquement en classe d'allocation statique). 

Exemples : 

_sfr P0; 

_sfrbit P0_6 _atbit( P0, 6 ); 

_bitword bw; /* bitaddressable word */ 

_bit myb _atbit( bw, 3 ); 

_inline 

→ définition de fonctions à utiliser intégrer directement dans le code, sans la procédure d'appel standard. 

Exemple : 

_inline int 

add( int a, int b ) 

{ 

return( a + b ); 

} 

void 

main( void ) 

{ 

int c = add( 1, 2 ); 

} 

_interrupt 

→ définition d'une fonction d'interruption 

Exemple : 

_interrupt( 0x22 ) void 

timer( void ) 

{ 

... 

}


#pragma asm 

→ insertion de lignes en assembleur 

terminé par #pragma endasm 

Syntaxe : 

#pragma asm [(pseudo_reg[=varname][, pseudo_reg[=varname]] ...)] 

#pragma endasm [(varname=pseudo_reg[, varname=pseudo_reg] ...)] 

avec : 

varname : nom d'une variable définie en C de type char ou int, signée ou non. 

pseudo_reg : registre écrit sous la forme @[w|b|i]num. num correspond à un numéro arbitraire de 

registre. Le compilateur choisira lui-même le registre adéquat. 

Registres utilisés 

Register 

Usage 

R0 

User Stack Pointer (USP) 

R1-R5, R10, R11 General registers (codegen, temporary results, C return values) 

R6-R9 

C register variables and saved register parameters 

R12-R15 

Fast C parameter passing and C register variables 

Paramètre renvoyé par une fonction : 

Return type Register(s) 

bit 

PSW.6 (USR0) 

char 

RL4 

short/int R4 

long 

R4-R5 (R4 low word, R5 high word) 

float 

R4-R5 

double user stack and R4 

structure R4 or R4-R5 (near or far address) 

near pointer R4 

far pointer R4-R5 (R4 page offset, R5 page number) 

huge pointer R4-R5 (R4 segment offset, R5 segment number) 

shuge pointer R4-R5 (R4 segment offset, R5 segment number) 

Fonctions intrinsèques 

→ fonctions prédéfinies. Évitent l'utilisation de l'assembleur. 

unsigned int _rol( unsigned int operand, unsigned int count ); 

unsigned int _ror( unsigned int operand, unsigned int count ); 

_bit _testclear( _bit semaphore ); 

_bit _testset( _bit semaphore ); 

_bit _getbit( BITADDR operand, ICE bitoffset ); 

void _putbit( _bit value, BITADDR operand, ICE bitoffset ); 

void _int166( ICE intno ); 

Exécute TRAP #intno 

void _idle( void ); 

void _nop( void ); 

void _pwrdn( void ); 

void _srvwdt( void ); 

Rafraîchit Watchdog 

void _diswdt( void ); 

Désactive Watchdog 

void _einit( void ); 

void _atomic( ICE number ); 

Portabilité 

→ inclure le fichier C166.h 

→ définit les extensions du langage pour les compilateurs autres que C166 

(Teste automatiquement le compilateur utilisé grâce à la macro prédéfinie _C166)


Code généré 

Observations générales 

#include 

//Code généré 

int fct(int a) 

{ 

return a*5; 

} 

main() 

{ 

int i,x; 

for(i=0; i


Utilisation de constantes 

#define Fcpu 20E6 

#define T0l 3 //Prédivision par 8 (2^3) 

#define FT0 (Fcpu/4/(1


Déclarations de données 

int decl(void) 

{ 

extern int strlen(const char *); 

static int x; 

int y; 

register z; 

char tab[]="toto"; 

register char *s="titi"; 

x=2; 

y=3; 

z=4; 

return x+y+z+strlen(s)+strlen(tab); 

} 

; essai.c 63 int decl(void) 

; essai.c 64 { 

PUBLIC _decl 

ESSAI_1_PR ENDS 

ESSAI_2_CO SECTION LDAT WORD PUBLIC 'CROM' 

_11_INIT LABEL BYTE 

DB 074h,06Fh,074h,06Fh,00h 

ESSAI_2_CO ENDS 

ESSAI_3_NB SECTION LDAT WORD PUBLIC 'CNEAR' 

ESSAI_3_NB_ENTRY LABEL BYTE 

_13 LABEL WORD 

DS 2 

ESSAI_3_NB ENDS 

ESSAI_1_PR SECTION CODE 

_decl PROC FAR 

SUB R0,#06h 

; Locals: 

; tab = offset 0 

; 

; Statics: 

; x = label _13 

; 

; CSEs: 

; s = R12 

; 

; essai.c 65 extern int strlen(const char 

*); 

; essai.c 66 static int x; 

; essai.c 67 int y; 

; essai.c 68 register z; 

; essai.c 69 char tab[]="toto"; 

MOV R4,#_11_INIT 

MOV R10,R0 

MOV R3,#05h 

CALLS SEG __cpnnb,__cpnnb 

; essai.c 70 register char *s="titi"; 

MOV R12,#_12 

; essai.c 71 x=2; 

MOV R13,#02h 

MOV _13,R13 

; essai.c 72 y=3; 

; essai.c 73 z=4; 

; essai.c 74 return 

x+y+z+strlen(s)+strlen(tab); 

MOV [-R0],R12 

MOV R12,#02h 

ADD R12,R0 

CALLS SEG _strlen,_strlen 

MOV [-R0],R4 

MOV R12,[R0+#02H] 

CALLS SEG _strlen,_strlen 

MOV R12,[R0+] 

ADD R0,#02h 

ADD R4,R12 

ADD R4,#09h 

; essai.c 75 } 

ADD R0,#06h 

RETS 

_decl ENDP


Elimination du code superflu 

//Variable x inutilisée 

void f1(int y) 

{ 

int x; 

x=4*y; 

} 

//Variable x inutilisée (volatile) 

void f2(int y) 

{ 

volatile int x; 

x=4*y; 

} 

//Elimination du code inutile 

int f3(int y) 

{ 

int a,b,c; 

a=3; 

b=4*a+2; 

c=(b


Utilisation de macros 

#define DIM(x) (sizeof(x)/sizeof(*x)) 

int Tab[10]; 

void InitTab(void) 

{ 

int i; 

for(i=0; i


Utilisation d'unions 

void PulseP2_3c(void) 

{ 

typedef union 

{ 

unsigned word_; 

struct {unsigned char lsb,msb;} byte_; 

struct 

{ 

unsigned b0:1; 





}bit_; 

}UWord; 

UWord *pUP2=(UWord*)(&P2); 

pUP2->bit_.b2=1; 

pUP2->bit_.b2=0; 

pUP2->byte_.msb=0x55; 

pUP2->bit_.b47=5; 

} 

void PulseP2_3d(void) 

{ 

static _sfrbit b2 _atbit(P2,2); 

b2=1; 

b2=0; 

_bfld(P2,0xFF00,0x5500); //P2H=55H 

_bfld(P2,0xFbit_.b47=5; 

MOV R13,[R12] 

BFLDL R13,#0F0h,#050h 

MOV [R12],R13 

; essai.c 134 } 

RETS 

_PulseP2_3c ENDP 

; essai.c 135 

; essai.c 136 void PulseP2_3d(void) 

; essai.c 137 { 

PUBLIC _PulseP2_3d 

_PulseP2_3d PROC FAR 

; Locals: 

; 

; Statics: 

; 

; CSEs: 

; 

; essai.c 138 static _sfrbit b2 

_atbit(P2,2); 

; essai.c 139 b2=1; 

BSET P2.2 

; essai.c 140 b2=0; 

BCLR P2.2 

; essai.c 141 _bfld(P2,0xFF00,0x5500); 

//P2H=55H 

BFLDH P2,#0FFh,#055h 

; essai.c 142 _bfld(P2,0xF


Fonctions _inline 

void inc(int *p) 

{ 

(*p)++; 

} 

_inline void inc_(int *p) 

{ 

(*p)++; 

} 

_inline int Add(int a, int b) 

{ 

return a+b; 

} 

int TestIncAdd1(void) 

{ 

int v1=2,v2=3,r; 

inc(&v1); 

inc_(&v1); 

r=Add(v1,v2); 

r+=Add(3,4); 

return r; 

} 

; essai.c 147 void inc(int *p) 

; essai.c 148 { 

PUBLIC _inc 

_inc PROC FAR 

; Locals: 

; 

; Statics: 

; 

; CSEs: 

; p = R12 

; 

; essai.c 149 (*p)++; 

MOV R13,[R12] 

ADD R13,#01h 

MOV [R12],R13 

; essai.c 150 } 

RETS 

_inc ENDP 

; essai.c 151 

; essai.c 152 _inline void inc_(int *p) 

; essai.c 153 { 

; essai.c 154 (*p)++; 

; essai.c 155 } 

; essai.c 156 

; essai.c 157 _inline int Add(int a, int b) 

; essai.c 158 { 

; essai.c 159 return a+b; 

; essai.c 160 } 

; essai.c 161 

; essai.c 162 int TestIncAdd1(void) 

; essai.c 163 { 

PUBLIC _TestIncAdd1 

_TestIncAdd1 PROC FAR 

SUB R0,#02h 

; Locals: 

; v1 = offset 0 

; 

; Statics: 

; 

; CSEs: 

; r = R12 

; v2 = R12 

; $inc_#1$p = R13 

; 

; essai.c 164 int v1=2,v2=3,r; 

MOV R12,#02h 

MOV [R0],R12 

MOV R12,#03h 

; essai.c 165 inc(&v1); 

MOV [-R0],R12 

MOV R12,#02h 

ADD R12,R0 

CALLS SEG _inc,_inc 

MOV R12,[R0+] 

; essai.c 166 inc_(&v1); 

MOV R13,R0 

MOV R14,[R13] 

ADD R14,#01h 

MOV [R13],R14 

; essai.c 167 r=Add(v1,v2); 

MOV R13,[R0] 

ADD R13,R12 

MOV R12,R13 

; essai.c 168 r+=Add(3,4); 

ADD R12,#07h 

; essai.c 169 return r; 

MOV R4,R12 

; essai.c 170 } 

ADD R0,#02h 

RETS 

_TestIncAdd1 ENDP 

; essai.c 171


int TestIncAdd2(void) 

; essai.c 172 int TestIncAdd2(void) 

{ 

; essai.c 173 { 

PUBLIC _TestIncAdd2 

int tb[]={0,1,2,3},*s=tb; ESSAI_1_PR ENDS 

int v1=2,v2=3,r; 

inc(s); 

ESSAI_2_CO SECTION LDAT 

inc_(s); 

EVEN 

_17_INIT LABEL WORD 

r=Add(v1,v2); 

DW 00h,01h,02h,03h 

r+=Add(3,4); 


return r; 

} 


_TestIncAdd2 PROC FAR 

SUB R0,#08h 

; Locals: 

; tb = offset 0 

; 

; Statics: 

; 

; CSEs: 

; s = R12 

; r = R12 

; 

; essai.c 174 int tb[]={0,1,2,3},*s=tb; 

MOV R4,#_17_INIT 

MOV R10,R0 

MOV R3,#08h 

CALLS SEG __cpnnb,__cpnnb 

MOV R12,R0 

; essai.c 175 int v1=2,v2=3,r; 

; essai.c 176 inc(s); 

MOV [-R0],R12 

CALLS SEG _inc,_inc 

MOV R12,[R0+] 

; essai.c 177 inc_(s); 

MOV R13,[R12] 

ADD R13,#01h 

MOV [R12],R13 

; essai.c 178 r=Add(v1,v2); 

; essai.c 179 r+=Add(3,4); 

MOV R12,#0Ch 

; essai.c 180 return r; 

MOV R4,R12 

; essai.c 181 } 

ADD R0,#08h 

RETS 

_TestIncAdd2 ENDP


Opérations : Calcul de a*b/c 

unsigned MulDivU1(unsigned a, 

unsigned b, unsigned c) 

{ 

return a*b/c; 

} 

unsigned MulDivU2(unsigned a, 


{ 

#pragma asm(@w1=a, @2=b, @3=c) 

MULU @1,@2 

DIVLU @3 

MOV @1,MDL 

#pragma endasm(a=@w1) 

return a; 

} 

_inline unsigned MulDivU3(unsigned 

a, unsigned b, unsigned c) 

{ 

#pragma asm(@w1=a, @2=b, @3=c) 

MULU @1,@2 

DIVLU @3 

MOV @1,MDL 

#pragma endasm(a=@w1) 

return a; 

} 

void TestMulDivU3(void) 

{ 

static int r; 

unsigned a=1000,b=200,c=127; 

r=MulDivU3(a,b,c); 

} 

; essai.c 185 unsigned MulDivU1(unsigned a, 


; essai.c 186 { 

PUBLIC _MulDivU1 

_MulDivU1 PROC FAR 

; Locals: 

; 

; Statics: 

; 

; CSEs: 

; b = R13 

; a = R12 

; c = R14 

; 

; essai.c 187 return a*b/c; 

MULU R12,R13 

DIVU R14 

MOV R4,MDL 

; essai.c 188 } 

RETS 

_MulDivU1 ENDP 

; essai.c 189 

; essai.c 190 unsigned MulDivU2(unsigned a, 


; essai.c 191 { 

PUBLIC _MulDivU2 

_MulDivU2 PROC FAR 

; @w1 = R12 

; @w2 = R13 

; @w3 = R14 

; Locals: 

; 

; Statics: 

; 

; CSEs: 

; a = R12 

; b = R13 

; c = R14 

; 

; essai.c 192 #pragma asm(@w1=a, @2=b, @3=c) 

MULU R12,R13 

DIVLU R14 

MOV R12,MDL 

; essai.c 196 #pragma endasm(a=@w1) 

MOV R13,R12 

; essai.c 197 return a; 

MOV R4,R12 

; essai.c 198 } 

RETS 

_MulDivU2 ENDP 

; essai.c 199 

; essai.c 200 _inline unsigned MulDivU3(unsigned a, 


; essai.c 201 { 

; essai.c 202 #pragma asm(@w1=a, @2=b, @3=c) 

; essai.c 203 MULU @1,@2 

; essai.c 204 DIVLU @3 

; essai.c 205 MOV @1,MDL 

; essai.c 206 #pragma endasm(a=@w1) 

; essai.c 207 return a; 

; essai.c 208 } 

; essai.c 209 

; essai.c 210 void TestMulDivU3(void) 

; essai.c 211 { 

PUBLIC _TestMulDivU3 


ESSAI_3_NB SECTION LDAT 


DS 2 



_TestMulDivU3 PROC FAR 

; @w1 = R13 

; @w2 = R14 

; @w3 = R15 

; Locals: 

; 

; Statics: 

; r = label _18 

;


; CSEs: 

; $MulDivU3#1$a = R12 

; a = R13 

; b = R14 

; c = R15 

; 

; essai.c 212 static int r; 

Interruptions 

_interrupt( 0x22 ) void ItTimer( void ) 

{ 

static int ct=0; 

ct++; 

} 

; essai.c 213 unsigned a=1000,b=200,c=127; 

MOV R13,#03E8h 

MOV R14,#0C8h 

MOV R15,#07Fh 

; essai.c 214 r=MulDivU3(a,b,c); 

MOV R12,R13 

MULU R13,R14 

DIVLU R15 

MOV R13,MDL 

MOV R12,R13 

MOV _18,R12 

; essai.c 215 } 

RETS 

_TestMulDivU3 ENDP 

; essai.c 218 _interrupt( 0x22 ) void 

ItTimer( void ) 

; essai.c 219 { 


ESSAI_IR_NB SECTION PDAT WORD PUBLIC 'CINITROM' 

ESSAI_IR_NB_ENTRY LABEL BYTE 

DW 00h 

ESSAI_IR_NB ENDS 

ESSAI_ID_NB SECTION LDAT WORD PUBLIC 

'CINITIRAM' 

ESSAI_ID_NB_ENTRY LABEL BYTE 


DS 2 

ESSAI_ID_NB ENDS 


_ItTimer PROC TASK ESSAI_TASK INTNO 

ESSAI_INUM = 022h 

PUSH DPP0 

MOV DPP0,#PAG ?BASE_DPP0 

PUSH DPP2 

MOV DPP2,#PAG ?BASE_DPP2 

NOP 

; Locals: 

; 

; Statics: 

; ct = label _19 

; 

; CSEs: 

; 

; essai.c 220 static int ct=0; 

; essai.c 221 ct++; 

SUB _19,ONES 

; essai.c 222 } 

POP DPP2 

POP DPP0 

RETI 

_ItTimer ENDP


Définition des constantes - Bilan 

ESSAI_3_NB SECTION LDAT 

_Tab LABEL WORD 

DS 20 

PUBLIC _Tab 


ESSAI_2_CO SECTION LDAT 

_4 LABEL WORD 

DW 040F0h,00h,00h,00h 

_7 LABEL WORD 

DW 040D3h,08800h,00h,00h 

_8 LABEL WORD 

DW 04050h,00h,00h,00h 

_12 DB 074h,069h,074h,069h,00h 


C166_US SECTION LDAT WORD GLBUSRSTACK 'CUSTACK' 

DS 58 

C166_US ENDS 

C166_INIT SECTION PDAT WORD GLOBAL 'CINITROM' 

DW 06h 

DPPTR ESSAI_ID_NB_ENTRY,ESSAI_IR_NB_ENTRY 

DW 02h 

C166_INIT ENDS 

C166_BSS SECTION PDAT WORD GLOBAL 'CINITROM' 

DW 05h,ESSAI_3_NB_ENTRY,018h 

C166_BSS ENDS 

$FLOAT(ANSI) 

EXTERN _strlen:FAR 

EXTERN __load8n:FAR 

EXTERN __cuf28r:FAR 

EXTERN __mlf8r:FAR 

EXTERN __dvf8r:FAR 

EXTERN __sbf8r:FAR 

EXTERN __cfu82r:FAR 

EXTERN __cpnnb:FAR 

EXTERN __CSTART:FAR 

REGDEF R0-R15 

; section name type alignment combine class length (hex) 

;============================================================================== 

; ESSAI_1_PR CODE WORD PUBLIC CPROGRAM 462 (0001CEh) 

; ESSAI_2_CO LDAT WORD PUBLIC CROM 43 (00002Bh) 

; ESSAI_3_NB LDAT WORD PUBLIC CNEAR 24 (000018h) 

; ESSAI_IR_NB PDAT WORD PUBLIC CINITROM 2 (000002h) 

; ESSAI_ID_NB LDAT WORD PUBLIC CINITIRAM 2 (000002h) 

; C166_US LDAT WORD GLBUSRSTACK CUSTACK 58 (00003Ah) 

; C166_INIT PDAT WORD GLOBAL CINITROM 12 (00000Ch) 

; C166_BSS PDAT WORD GLOBAL CINITROM 6 (000006h) 

END

Système cible C167CR - 83 - 

Starter kit STK16x500 

http://www.tq-group.com 

Strap X1 Function 

ON VBAT connected to Battery for SRAM Backup Strap 

OFF VBAT not connected to Battery 

X2-Connector: RS232 X4-Connector: CAN 1 + 2 

Pin-No Function Pin-No Function 

1 n.c. 1 CAN2_L 

2 RxD# 2 CAN1_L 

3 TxD# 3 DGND 

4 DTR / BOOTSTR# 4 CAN2_H 

5 DGND 5 n.c. 

6 n.c. 6 DGND 

7 RTS / RESINS# 7 CAN1_H 

8 n.c. 8 n.c. 

9 n.c. 9 VCC5V


X5-Connector: Steppermotor 

Pin-No Function 

6 MOT2B_T 

5 MOT2A_T 

4 VCC12V 

3 MOT1B_T 

2 MOT1A_T 

1 VCC12V 

X6-Connector: Port P3.x 


1 P3.0 2 P3.1 

3 P3.2 4 P3.3 

5 P3.4 6 P3.5 

7 P3.6 8 P3.7 

9 P3.8 10 P3.9 

11 P3.10 12 P3.11 

13 P3.12 14 P3.13 

15 VCC5V 16 DGND 


Pin-No Function 

1 P2.0 

2 P2.1 

3 P2.2 

4 P2.3 

5 P2.4 

6 P2.5 

7 P2.6 

8 P2.7 



1 P5.0 2 P5.1 

3 P5.2 4 P5.3 

5 P5.4 6 P5.5 

7 P5.6 8 P5.7 


X13-Connector: Port P7.0 


1 P7.0 2 P7.1 

3 P7.2 4 P7.3 

5 P7.4 6 P7.5 

7 P7.6 8 P7.7 




1 P8.0 2 P8.1 

3 P8.2 4 P8.3 

5 P8.4 6 P8.5 

7 P8.6 8 P8.7 


S4-Switch 4: Bootstrap Loader 

Switch-Pos Function 

OFF Set TQMinimodul to normal Mode 

ON Set TQMinimodul to Bootstrap Loader Mode (not used with TQ Download Tools

Système cible C167CR - 85 -




Minimodule TQM167C 

TQM167C-AB REV.601 

http://www.tqc.de


Microcontroller SAB-C167-LM / SAB-167CR-LM 

• High Performance 16 Bit-CPU 

• 100 ns Instruction Cycle Time at 20 MHz CPU 

• Up to 16 MByte Linear Address Space for Code and Data 

• On-Chip CAN Interface (Version 2.0B) (*only SAB-C167CR-LM) 

• 16-channel 10-bit A/D Converter 

• Two 16-Channel Capture/Compare Units 

• 4-Channel PWM Unit 

• Two Multi-Functional General Purpose Timer Units with five 16-bit Timers 

• Programmable Watchdog Timer 

• Two Serial Channels (Synchronous/Asynchronous and High-Speed Synchronous) 

• On-Chip Bootstrap Loader 

Memory 

• Flash-Memory 

256 kByte or 1 MByte 

organization 128k*16 or 512k*16 

90 ns access time 

on Board programmable 

Standard: 256 kByte 

• SRAM-Memory 

256 kByte or 1 MByte 

organization 128k*16 or 512k*16 

70 ns access time 

external battery backup 

Standard: 256 kByte 

Reset-Logic 

• CPU internal Watchdog 

External Watchdog 

Switchable by Software (Optional) 

Power-Fail Logic with MAX691 

Interface 

• Serial-Interface 

one internal asynchronous (integrated in the processor) 

used unbuffered as RxD0 and TxD0 

with RS232 Driver as RxD0# and TxD0# 

one external asynchronous (external UART COM81C17) 

one internal synchronous (integrated in the processor) 

• Bus-Interface 

Address Bus 

Data Bus 

Control Bus 

Fast 74ACTQ Drivers 

• Internal Bootstrap Loader 

Download via serial Interface 

Download via Bootstrap Loader Connector 

Powerful Download Tools 

Download to SRAM or Flash 

Internal LED 

The LED installed on the top of the module is connected to the reset output RSOUT# of the module. It 

lights when RSOUT# is active, i.e. until the EINF command has been executed after a reset.


Model No. and Order Code 

TQM167 C X Y Minimodul 

Optional Function 

total 

No Option (Standard) add 0 

External Watchdog activ add 1 

Without RS232 Driver add 2 

Without 2. Serial Interface add 4 

Without Connector X2 for P7.x lines add 8 

Without external Address lines A0...A15 add 16 

Without external Bus Interface add 32 

Summary Y = 

Memory X = 256 kByte SRAM 1 Mbyte SRAM 

256 kByte FLASH A* B 

1 Mbyte FLASH C D 

* Standard 

CAN Configuration C = 

With SAB-C167LM / without CAN Blank 

With SAB-C167CR-LM / with CAN C 

Memory Management 

This section contains all details and the know-how necessary for optimum usage of the memory installed 

in the module. The memory range management and configuration (memory management) can be 

implemented entirely by software. The address ranges can be programmed flexibly with the 5 freely 

programmable CS outputs of the processor and the associated configuration registers. 

Principle of operation 

The microcontroller SAB-C167 is equipped with 5 freely programmable Chip Select outputs which allow 

access to the respective periphery. For each address block allocated to a Chip Select output, it is also 

possible to select an individual configuration of the system bus. For this, the bus type, bus width, wait 

states and also the memory block can be allocated to a CS signal. 

CS0 addresses all memory blocks of the addressable range not allocated to CS1-CS4. This makes it 

possible to manage non-sequential memory blocks without further measures. After a reset, the Chip 

Select lines CS1-CS4 of the processor are inactive. In this case, CS0 is active for the entire memory 

range. 

To allow programs in the flash EPROM to be started, CS0 is used to address these memory chips after a 

reset CS0.


Chip Select allocation 

The memory configuration applicable in most cases is works-adjusted by the manufacturer: 

· CS0 addresses the flash EPROMs, 

· CS1 the SRAMs. 

If external memory is to be superimposed on the address range of the SRAM or flash EPROM, the 

SRAM / flash EPROM must be accessed through CS0 because it is only possible to open "windows" on 

memory blocks accessed by CS0. 

To switch between the CS lines CS0 and CS1, an external register names XREG is implemented. XREG 

is accessed by CS2# and address line A8. Switching is performed with the data lines D0 and D1. 

Standard settings by TQ-Components : 

Control line 

Connected chip 

CS0# On-board flash EPROM or on-board SRAM *) 

CS1# On-board flash EPROM or on-board SRAM *) 

CS2# 

Additional asynchronous interface and XREG 

CS3# 

External memory 

CS4# 

External memory 

CS0# Reset configuration 000000h- FFFFFFh Flash EPROM 

*) Switchable with XREG 

Programming of the Chip Select lines 

The Chip Select lines are programmed by software via the registers BUSCON0..4 and ADDRSEL1..4. 

The BUSCON registers define the hardware configuration of the system bus, the ADDRSEL registers the 

scope and size of memory. 

In this, it must be observed that ADDRSEL0 does not exist because, as described in Sect. xx, all memory 

space outside the defined ranges of CS1-CS4 is allocated to the Chip Select line CS0. 

BUSCON registers: 

The BUSCON registers are all adjustable by software. These are not preset apart from the BUSCON0 

register. 

The following parameter can be set individually through the BUSCON registers for each memory block 

initialised with the respective CS lines: 

- Bus width : 

The system bus can be selected with a width of 8 or 16 bits. If an 8-bit bus is selected, first 

the Low byte and then the High byte are transferred through the data lines D0-D7. 

- Bus type : 

This allows the selection of a multiplexed or non-multiplexed bus. 

- Wait states : 

Up to 15 wait states, memory tristates and a R/W delay can be specified. 

- Miscellaneous : 

The length of the ALE signal and the functions of RD# and WR# can also be influenced 

here. The exact programming is to be found in the processor manual (page 63).


ADDRSEL registers: 

The division of the memory range is performed with the ADDRSEL registers. For this, the starting 

address of the memory block and the memory size must be specified (page 64). 

- Range Start Address (RGSAD) : 

specifies the starting address of the memory block for the respective CS line (only integer 

multiples of the adjusted block size (RGSZ) are valid as the starting address; see table). 

- Range Size Selection (RGSZ) : 

Specifies the memory size as shown in the table below. 

RGSZ: Memorysize RGSAD: Startaddress 

0 0 0 0 4 Kbyte RRRRRRRRRRRRb RRRRRRRRRRRRb * 4KByte 

0 0 0 1 8 Kbyte RRRRRRRRRRRxb RRRRRRRRRRR0b * 4KByte 

0 0 1 0 16 Kbyte RRRRRRRRRRxxb RRRRRRRRRR00b * 4KByte 

0 0 1 1 32 Kbyte RRRRRRRRRxxxb RRRRRRRRR000b * 4KByte 

0 1 0 0 64 Kbyte RRRRRRRRxxxxb RRRRRRRR0000b * 4KByte 

0 1 0 1 128 Kbyte RRRRRRRxxxxxb RRRRRRR00000b * 4KByte 

0 1 1 0 256 Kbyte RRRRRRxxxxxxb RRRRRR000000b * 4KByte 

0 1 1 1 512 Kbyte RRRRRxxxxxxxb RRRRR0000000b * 4KByte 

1 0 0 0 1 MByte RRRRxxxxxxxxb RRRR00000000b * 4KByte 

1 0 0 1 2 MByte RRRxxxxxxxxxb RRR000000000b * 4KByte 

1 0 1 0 4 MByte RRxxxxxxxxxxb RR0000000000b * 4KByte 

1 0 1 1 8 MByte Rxxxxxxxxxxxb R00000000000b * 4KByte 

Rest : Not defined 

R : used bit 

x : unused bit 

Example : 

ADDRSEL4 = 0x1A42; (= 0001 1010 0100 0010b) 

Specifies a 16 KByte block of memory from address 1A4000h for access to external memory. 

Programming the XREG register 

With the aid of the external register XREG, it is possible to switch between the Chip Select lines CS0# 

and CS1#. 

The register XREG is selected when both the address line A8 and the Chip Select line CS2# reach a Low 

state. Only then is it possible to program the two Chip Select lines by the data lines D0 and D1. In this, 

XREG.D0 switches CS#1 and XREG.D1 switches CS#0: 

The following table is intended to simplify programming : 

XREG CS-Line: CS-Line: 

D1 D0 CS0# CS1# 

0 0 Flash Flash 

0 1 Flash SRAM Default-Value 

1 0 SRAM Flash 

1 1 SRAM SRAM


XREG can only be changed after it has been initialised by EINIT (machine command, see processor 

manual) (RSTOUT# º High). If XREG is accessed in word mode, the High byte must also contain the 

value of XREG because CS2# is initialised as an 8-bit bus and the High byte is also written to XREG. 

XREG access times : 

The configuration register XREG is implemented with a simple JK flipflop and can only be accessed for 

writing. XREG cannot be read. Access is fully uncritical and can therefore be executed with 0 wait states. 

Examples : 

• ADDRSEL2 = 2000h 

then : 

UART address = 200100h XREG address = 200200h 

• The program is located in the SRAM and is accessed via CS1#. CS0# is to be selected : 

XREG = 1 1 CS0# and CS1# access the SRAM. 

BUSCON0 = < SRAM configuration > Prepares switching for CS0# 

ADDRSEL1 = < Flash memory range > Deactivates the address range for CS1# 

==> Program "runs" via CS0# 

BUSCON1 = Access to the flash is initialised 

XREG = 0 1 CS1# is allocated to the flash 

Internal bootstrap loader 

The installed processor is equipped with a bootstrap loader which, in conjunction with the periphery 

implemented in the module, makes programming of the EPROMs unnecessary. 

The downloading of a program to the module can be performed via the serial interface or via the separate 

connector on the top of the TQM167 module. The download interface is connected directly to the serial 

interface of a PC. 

In this way, programs can be downloaded from a PC without additional hardware, either to the SRAM or 

to the flash EPROM. 

Because the internal bootstrap loader of the processor can only process 32 bytes, it is necessary to transfer 

programs in several blocks into the memory of the module. 

Functional sequence: 

1. To activate the bootstrap loader, a reset must first be initiated (RTS and DTR active = 1). 

2. The reset is enables after approx. 10 ms, the DTR line remains active. 

3. The processor then enters the bootstrap loader mode and waits for a Null byte transmitted via 

ASC0. 

4. The processor then returns an acknowledgement byte ($A5), which can be used to identify the 

processor. 

5. 32 bytes are then transmitted by the PC, which are loaded directly into the internal RAM of the 

processor. 

To allow convenient downloading of programs with larger memory requirement, TQ has developed the 

program BOOT16x (DOS Version) and TQLoad (Windows Version). 

The program BOOT16x provides user-friendly control of the entire loading operation. More detailed 

explanations and examples of this are to be found in the Software Manual.


The following signal lines of the serial interface are used (by the PC) for the download : 

TQM167 PC (DSUB-9) PC (DSUB-25) 

Signal Pin Pin Signal Pin Signal 

RESINS# 1 ↔ 7 RTS 4 RTS 

TXD0# 2 ↔ 2 RxD 3 RxD 

GND 3 ↔ 5 GND 7 GND 

GND 4 ↔ 5 GND 7 GND 

BOOTSTR# 5 ↔ 4 DTR 20 DTR 

RXD0# 6 ↔ 3 TxD 2 TxD 

Power fail supervisor 

The MAX691 chip is installed as a power fail supervisor. This monitors the supply voltage and initiates a 

controlled reset of the module if the voltage falls. Special hardware (power fail logic) is implemented in 

the module for this purpose. 

Another task of the chip is to protect the SRAMs against data loss. For this, the chip switches the supply 

voltage of the SRAMs to the battery supply and protects the SRAM against uncontrolled access by the 

processor. 

Technical Data 

PCB-Material: 

FR4 

PCB-Layout: 

double sided SMT 

PCB-Layer: 

6 Layer 

Dimension: 

81,6 x 54 mm² 

Ambient Operating Temperature: 0°C - 70°C 

Storage Temperature Range: -20°C - +85°C 

Power Supply: 5 VDC ± 5% 

Power Dissipation 

typ. 250 mA


Connecteurs 

Extension Connector X2 

No.: Function No.: Function No.: Function No.: Function 

1 P7.0 3 P7.2 5 P7.4 7 P7.6 

2 P7.1 4 P7.3 6 P7.5 8 P7.7 

Bootstraploader Connector X3 

No.: Function No.: Function No.: Function 

1 RESINS# 3 DGND 5 BOOTSTR# 

2 TxD0# 4 DGND 6 RxD0# 

Interface Connector X1 

Pin- Function Pin- Function Pin- Function Pin- Function 

No.: No.: No.: No.: 

128 P3.1/T6OUT 96 P3.0/T0IN 64 DGND 32 DGND 

127 P3.3/T3OUT 95 P3.2/CAPIN 63 P5.8 31 P5.9 

126 P3.5/T4IN 94 P3.4/T3EUD 62 P5.6 30 P5.7 

125 P3.7/T2IN 93 P3.6/T3IN 61 Varef 29 AGND 

124 RXD1 92 TXD1 60 P5.4 28 P5.5 

123 P3.11/RXD0 91 P3.10/TXD0 59 P5.2 27 P5.3 

122 READY# 90 NC 58 P5.0 26 P5.1 

121 P3.15 89 P2.1 57 P5.15 25 RSIN# 

120 P2.0 88 P2.3 56 P5.13 24 P5.14 

119 P2.2 87 P2.5 55 P5.11 23 P5.12 

118 P2.4 86 P2.7 54 NC 1 /CAN_RXD 2 22 P5.10 

117 P2.6 85 P2.9 53 NC 1 /CAN_TXD 2 21 Vbat 

116 P2.8 84 P2.11 52 P8.7 20 P8.6 

115 P2.10 83 P2.13 51 P8.5 19 P8.4 

114 P2.12 82 P2.15 50 P8.3 18 P8.2 

113 P2.14 81 A17 49 P8.1 17 P8.0 

112 A16 80 WR# 48 NMI# 16 RSOUT# 

111 RD# 79 ALE 47 P6.5/HOLD# 15 P6.7/BREQ# 

110 BHE# 78 P3.8/MRST 46 A7 14 P6.6/HLDA# 

109 P3.13/SCLK 77 P3.9/MTSR 45 A6 13 A5 

108 D7 76 D6 44 A4 12 A3 

107 D5 75 D4 43 A2 11 A1 

106 D3 74 D2 42 A0 10 A23 1 

105 D1 73 D0 41 CSE# 9 A22 1 

104 CSE1# 72 CSE2# 40 A21 1 8 A20 1 

103 RESINS# 71 BOOTSTR# 39 A19 7 A18 

102 CP1# 70 CP2# 38 A15 6 A14 

101 D14 69 D15 37 A13 5 A12 

100 D12 68 D13 36 A11 4 A10 

99 D10 67 D11 35 A9 3 A8 

98 D8 66 D9 34 TXD0# 2 RXD0# 

97 Vcc 65 Vcc 33 TXD1# 1 RXD1# 

1 = only for TQM167 

2 = only for TQM167C

Tasking EDE C167CR - 96 - 

Environnement Tasking 

→ Tasking EDE (Embedded Development Environment) 

• Créer un répertoire de travail 

• Exécuter sous Windows l'application EDE C166_ST10 ( à partir du bureau). 

• Faire File->Change Directory et sélectionner le répertoire préalablement créé. 

• Faire Project->Project Space ->New. 

Entrer le nom de l'espace de projets à créer (sans extension) 

• Dans la fenêtre qui s'ouvre, créer un nouveau projet en sélectionnant l'icône (Add New Project 

to Project Space). Donner un nom à ce projet (sans extension). 

• Créer maintenant un nouveau fichier en cliquant sur l'icône (Add New File To Project). Donner 

un nom à ce fichier, avec une extension ".c". 

• Cliquer sur Ok. 

→ Le nouveau fichier est prêt à être édité. 

• Écrire le programme et l'enregistrer. 

• Faire EDE->Project Options. 

Dans CPU, sélectionner le C167CR et faire Ok. 

• Lancer la compilation en cliquant sur l'icône (Execute Compile Command). 

Noter la différence obtenue avec (Execute Make Command) et (Execute Rebuild 

Command). 

• S'il n'y a pas d'erreur, faire EDE->CrossView Pro Options et sélectionner Simulator. Faire 

Ok. 

Lancer le debugger Crossview en cliquant sur (Debug Application). 

Exécuter le programme en pas à pas, en observant le code exécuté et l'état des variables et des 

registres du CPU. 

• Si la carte cible est reliée, faire EDE->CrossView Pro Options et sélectionner 

ROM/RAM Monitor. Choisir la cible (target) TQ components TQM167C. 

Exécuter ensuite Crossview comme précédemment.


Applications 

Chenillard 

Réaliser un chenillard sur les 16 LEDs de la carte d'application. 

Temporisations 

Réaliser les fonctions DelayUs et DelayMs selon les prototypes ci-dessous : 

void DelayUs(unsigned dt); // délai en µs 

void DelayMs(unsigned dt); // délai en ms 

On utilisera pour cela le timer T5 sans interruptions. 

Quelles sont les limitations rencontrées ? 

On autorisera des variations de dt entre 0 et 65535. 

Convertisseur analogique 

Faire un programme qui lit en permanence le CAN sur le canal 0. 

Afficher le résultat sur l'afficheur LCD sous la forme 0.000 V. 

On utilisera pour cela les fonctions suivantes : 

- void lcd_strout(const char *) 

- void lcd_init(void) 

- void lcd_clr(void) 

- void lcd_home(void) 

Signal PWM 

Générer un signal PWM variable en fonction de la tension présente sur le canal 0 du CAN. 

Mettre en œuvre un signal permettant d'obtenir 256 niveaux de tension, puis 1024 niveaux de tension. 

Dans chacun des cas, indiquer la fréquence de hachage obtenue. 

Génération et mesure de signaux 

Générer le signal A en utilisant CAPCOM0. 

On reçoit le signal B sur CAPCOM1. 

Mesurer la valeur de ∆t (comprise entre 1 ms et 30 ms) 

avec une précision maximale. Indiquer sa valeur sur 

l'afficheur LCD. 

Quelle est la résolution obtenue ? 

Réaliser cette mesure toutes les 100 ms. 

A 

B 

1ms 

∆t 

1ms


Limiteur d'accélération pour la commande de moteur 

→ limitation du couple d'accélération 

→ limitation des courants 

v k : vitesse souhaitée 

v' k : vitesse obtenue 

DT : période d'échantillonnage 

v k 

Accélération max 

v' k 

v k 

dv MAX 

v k-1 

Exemple : 

Fréquence de hachage = 10kHz 

v max = 254 

accélération arrêt / pleine vitesse en 1mn (dv=127 en 60s) 

⇒ DT = 0,1 ms et dv MAX = 212.10 -6 

DT 

v codé sur 1 octet (0 à 255) 

→ peut être codé sur 32 bits en multipliant par 2 24 : 

On note V = v.2 24 

⇒ DV MAX = dv MAX .2 24 = 212.10 -6 .16777216 ≈ 3551 

v 00 H 00 H 00 H 

V 

Dans le bloc limiteur d'accélération, on travaille avec V et DV : 

(exemple pour la limitation en vitesse croissante) 

consigne v k ⇒ V k 

si V k > V k-1 + DV max 

V k = V k-1 + DV max 

extraction de v' k à partir de V k ⇒ application de la nouvelle commande 

Rem. : V k-1 : valeur précédente de V k → utilisation d'une variable statique.

16C73A PIC - 99 - 

MICROCONTROLEURS PIC 

I. PIC 16C73A 

I.1. Caractéristiques générales 

- CPU RISC 

- 35 instructions exécutées en 1 cycle (200ns) 

- DC à 20MHz 

- faible consommation (

16C73A PIC - 100 - 

I.3.b. Pile 

- Ne fait pas partie de la mémoire programme ni de la mémoire de données 

- SP ne peut être ni lu, ni modifié 

- contient 8 mots de 13 bits 

- affectée par CALL, RETURN, RETLW, RETFIE ou interruption 

ATTENTION : 

- la pile fonctionne comme un buffer circulaire sur 8 niveaux 

→ quand niveau ≥8, le niveau 0 est écrasé 

I.3.c. Mémoire de données 

Organisée en 2 banques de 128 octets (00h à 7Fh) 

Choix de la banque : bit RP0 de STATUS (STATUS.5) : 

- STATUS.5 = 0 : banque 0 [00h … 7Fh] 

- STATUS.5 = 1 : banque 1 [80h … FFh] 

Les SFRs sont aux adresses basses de chaque banque. 

Certains SFRs sont communs aux 2 banques (ex : STATUS) 

sur PIC16C73A : 

SFRs : 00h … 1Fh et 80h … 9Fh 

RAM : 20h … 7Fh et A0h … FFh (registres à usage général) 

File Address File Address 

00h INDF (1) INDF (1) 80h 

01h TMR0 OPTION 81h 

02h PCL PCL 82h 

03h STATUS STATUS 83h 

04h FSR FSR 84h 

05h PORTA TRISA 85h 

06h PORTB TRISB 86h 

07h PORTC TRISC 87h 

08h PORTD (2) TRISD (2) 88h 

09h PORTE (2) TRISE (2) 89h 

0Ah PCLATH PCLATH 8Ah 

0Bh INTCON INTCON 8Bh 

0Ch PIR1 PIE1 8Ch 

0Dh PIR2 PIE2 8Dh 

0Eh TMR1L PCON 8Eh 

0Fh TMR1H 8Fh 

10h T1CON 90h 

11h TMR2 91h 

12h T2CON PR2 92h 

13h SSPBUF SSPADD 93h 

14h SSPCON SSPSTAT 94h 

15h CCPR1L 95h 

16h CCPR1H 96h 

17h CCP1CON 97h 

18h RCSTA TXSTA 98h 

19h TXREG SPBRG 99h 

1Ah RCREG 9Ah 

1Bh CCPR2L 9Bh 

1Ch CCPR2H 9Ch 

1Dh CCP2CON 9Dh 

1Eh ADRES 9Eh 

1Fh ADCON0 ADCON1 9Fh 

20h 

A0h 

General 

Purpose 

Register 

General 

Purpose 

Register 

Unimplemented data memory locations, read as '0'. 

7Fh FFh 

Bank 0 Bank 1

16C73A PIC - 101 - 

Note 1: 

Note 2: 

Not a physical register. 

These registers are not physically implemented on the PIC16C73/73A, read as '0'. 

I.4. Registres du processeur 

STATUS 

- positionné par ALU (C, DC, Z) 

- sélection des banques mémoires de données (RP0) 

IRP RP1 RP0 nT0 nPD Z DC C 

- IRP, RP1 : inutilisés, laisser à 0 

- RP0 : sélection des banques mémoires de données 

- nT0 : Time Out bit ; lecture seule 

→ 1 au démarrage, ou instruction CLRWDT ou SLEEP 

→ 0 si watchdog time-out. 

- nPD : Power Down bit ; lecture seule 

→ 1 : au démarrage ou instruction CLRWDT 

→ 0 : instruction SLEEP 

- Z : Résultat nul (ALU) 

- DC : demi retenue ALU (à appliquer sur bit b4 du résultat) 

- C : retenue ALU 

INTCON 

- contrôle d'interruption & évènements sur les périphériques ; en lecture / écriture 

GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 

- GIE : autorise [1] ou interdit [0] toutes les interruptions 

- PEIE : autorise [1] ou interdit [0] les interruptions des périphériques non masqués 

- TOIE : autorise [1] ou interdit [0] l'interruption sur débordement timer 0 (TMR0) 

- INTE : autorise [1] ou interdit [0] l'interruption externe 

- RBIE : autorise [1] ou interdit [0] l'interruption sur un changement d'état du port RB 

- TOIF : indicateur débordement [1] sur timer 0 (TMR0) 

- INTF : indicateur interruption externe [1] 

- RBIF : positionné à 1 si un bit du port RB parmi RB4…RB7 a changé 

TOIF, INTF et RBIF 

doivent être remis à 0 par logiciel. 

PIE1, PIE2 

- autorisation des interruption des périphériques 

PIR1, PIR2 

- indicateurs d'identification des interruptions des périphériques 

PCON 

Power Control 

permet de distinguer : 

- POR (Power On Reset) 

généré quand V DD croît et passe le seuil d'environ 1.5V à 2.1V. 

La patte MCLR étant reliée à V DD via une résistance de tirage, POR indique la mise sous 

tension du système. 

- MCLR Reset (Master Reset, sur entrée externe) 

- WDT (WatchDog) Reset 

- BOR (Brown Out Reset) 

déclenché suite à une chute de la tension d'alimentation qui atteint environ 4V (de 3.8V à 

4.2V), pendant un certain temps. 

Au démarrage, plusieurs configurations peuvent être observées :

16C73A PIC - 102 - 

POR BOR TO PD 

PCON.1 PCON.0 STATUS.4 STATUS.3 

0 x 1 1 Mise sous tension du système 

1 0 x x Chute de la tension d'alimentation 

1 1 0 1 WatchDog reset 

1 1 0 0 Réveil par Watchdog 

1 1 1 1 Reset externe activé (patte MCLR) 

1 1 1 0 Sortie de SLEEP par MCLR ou 

interruption 

PCL et PCLATH 

PC est un registre 13 bits constitué de PCLATH (PC.12 à PC.8) et PCL (PC.7 à PC.0). 

b4 

b0 b7 

b0 

PCLATH 

PCL 

Utilisation : 

- GOTO calculé. 

Ex. : ADDF PCL,1 (Ajoute W et PCL ; résultat dans PCL) 

PCL : registre 8 bits ⇒ bloc de 256 octets disponible 

- instructions CALL et GOTO 

→ opérandes sur 11 bits ⇒ permet l'accès à 2K-mots de mémoire 

→ insuffisant pour le PIC16C73A 

→ les bits PCLATH.3 et PCLATH.4 sont utilisés pour constituer le PC 

→ doivent être positionnés avant l'utilisation de CALL ou GOTO 

- RETURN 

ne modifie pas PCLATH 

Le mot de 13 bits contenu dans la pile est directement transféré dans PC sans affecter 

PCLATH. 

INDF et FSR 

Utilisés pour l'adressage indirect 

INDF n'est pas un registre physique (implanté à l'adresse 0) 

Quand une instruction utilise INDF, elle utilise l'octet pointé par FSR. 

Exemple : remise à 0 d'une zone mémoire comprise entre 20h et 2Fh : 

20h → FSR 

tant que FSR < 30h 

0 → INDF écriture dans INDF ⇒ écriture dans [FSR] 

FSR+1 → FSR 

I.5. Programmation 

I.5.a. Instructions sur octets 

'f' : registre (file register), de 0 à 7Fh 

'd' : destination 

si d=0 → résultat dans W 

si d=1 → résultat dans 'f' 

Exemples : 

CLRF 

DECF CNT,1 CNT-1 → CNT 

DECF CNT,0 CNT-1 → W 

ENCORE DECFSZ REG,1 décrémente REG ; SKIP * si Zéro

16C73A PIC - 103 - 

GOTO ENCORE brancher à ENCORE si REG ≠ 0 

SUITE 

SWAP RG1,1 si RG1=F4h ⇒ RG1=4Fh 

SUBWF AB,1 AB-W → W ; C=1 si résultat ≥ 0 

(*) : n'exécute pas l'instruction suivante. 

I.5.b. Instructions sur bits 

'b' : numéro du bit affecté par l'opération (0 à 7) 

'f' : registre 

Exemples : 

BCF REG,3 met à 0 le bit 3 de REG 

BTFSC CNT,7 test du bit 7 de CNT ; SKIP si = 0 

I.5.c. Opérations littérales et de contrôle 

'k' : constante de 8 ou 11 bits, ou valeur littérale 

Exemples : 

ADDLW 23 

W+23 → W ; k sur 8 bits 

CALL TOTO appel du sous programme TOTO ; k sur 11 bits 

GOTO SUITE 

MOVLW 0x03 

03h → W 

CLRWDT 

remise à 0 du Watchdog 

SLEEP 

mise en veille (réveil par RESET, iT ou WDT) 

RETLW 0x12 

⇔ W=12h ; RETURN 

Utilisation de RETLW (lecture d'une donnée en mémoire programme) : 

MOVLW 5 

CALL TABLE 

……….. 

TABLE 

ADDWF PC 

RETLW CT1 CT1 : valeur retournée si W=1 



………..

16C73A PIC - 104 - 

Mnemonic Operands Description Cycles 

MSb 

14-Bit Opcode 

LSb 

Status 

Affected 

Notes 

BYTE-ORIENTED FILE REGISTER OPERATIONS 

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 

ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 

CLRF f Clear f 1 00 0001 lfff ffff Z 2 

CLRW - Clear W 1 00 0001 0xxx xxxx Z 

COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 

DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 

DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 

INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 

IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 

MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 

MOVWF f Move W to f 1 00 0000 lfff ffff 

NOP - No Operation 1 00 0000 0xx0 0000 

RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 

RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 

SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 

SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 

XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 

BIT-ORIENTED FILE REGISTER OPERATIONS 

BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 

BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 

BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 

LITERAL AND CONTROL OPERATIONS 

ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z 

ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z 

CALL k Call subroutine 2 10 0kkk kkkk kkkk 

CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD 

GOTO k Go to address 2 10 1kkk kkkk kkkk 

IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z 

MOVLW k Move literal to W 1 11 00xx kkkk kkkk 

RETFIE - Return from interrupt 2 00 0000 0000 1001 

RETLW k Return with literal in W 2 11 01xx kkkk kkkk 

RETURN - Return from Subroutine 2 00 0000 0000 1000 

SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD 

SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z 

XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z 

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. 

For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 

Note 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 

Note 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

16F628 PIC - 105 - 

II. PIC 16F628 

FLASH-Based 8-bit CMOS Microcontroller 

II.1. Présentation générale 

Caractéristiques 

• CPU RISC 

• 35 instructions (exécutées en 200ns) 

• fonctionnement statique à 20 MHz 

• 2 K-mots mémoire programme (FLASH) 

• 224 octets RAM 

• 128 octets EEPROM 

• 15 lignes d’Entrées/sorties 

• Module comparateur analogique 

• 3 timers (deux 8 bits et un 16 bits) 

• module capture/comparaison/PWM 

• USART 

Fonctionnement de 3.0 à 5.5V (version F) ou 2.0 à 5.5V (LF) 

Consommation : 

< 2 mA en 5V, 4MHz 

15 µA en 3V, 32kHz 

< 1 µA en standby (3V) 

Brochage

16F628 PIC - 106 - 

Description du brochage 

Name 

DIP I/O/P Buffer 

Pin # Type Type 

Description 

RA0/AN0 17 I/O ST Bi-directional I/O port/Analog comparator input 

RA1/AN1 18 I/O ST Bi-directional I/O port/Analog comparator input 

RA2/AN2/VREF 1 I/O ST Bi-directional I/O port/Analog comparator input/VREF out-put 

RA3/AN3/CMP1 2 I/O ST Bi-directional I/O port/Analog comparator input/comparator output 

RA4/T0CKI/CMP2 3 I/O ST Bi-directional I/O port/Can be configured as T0CKI/com-parator output 

RA5/MCLR/THV 4 I ST 

Input port/master clear (reset input/programming voltage input. When configured as MCLR, 

this pin is an active low reset to the device. Voltage on MCLR/THV must not exceed VDD 

during normal device operation. 

RA6/OSC2/CLKOUT 15 I/O ST 

Bi-directional I/O port/Oscillator crystal output. Connects to crystal or resonator in crystal 

oscillator mode. In ER mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of 

OSC1, and denotes the instruction cycle rate. 

RA7/OSC1/CLKIN 16 I/O ST Bi-directional I/O port/Oscillator crystal input/external clock source input. ER biasing pin. 

RB0/INT 6 I/O TTL/ST (1) Bi-directional I/O port/external interrupt. Can be software programmed for internal weak pullup. 

RB1/RX/DT 7 I/O TTL/ST (3) Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be software 

programmed for internal weak pull-up. 

RB2/TX/CK 8 I/O TTL/ST (3) Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be software 

programmed for internal weak pull-up. 

RB3/CCP1 9 I/O TTL/ST (4) Bi-directional I/O port/Capture/Compare/PWM I/O. Can be software programmed for internal 

weak pull-up. 

RB4/PGM 10 I/O TTL/ST (5) change. Can be software programmed for internal weak pull-up. When low voltage 

Bi-directional I/O port/Low voltage programming input pin. Wake-up from SLEEP on pin 

programming is enabled, the interrupt on pin change and weak pull-up resistor are disabled 

RB5 11 I/O TTL 

Bi-directional I/O port/Wake-up from SLEEP on pin change. Can be software programmed for 

internal weak pull-up. 

RB6/T1OSO/T1CKI 12 I/O TTL/ST (2) Bi-directional I/O port/Timer1 oscillator output/Timer1 clock input. Wake up from SLEEP on 

pin change. Can be software programmed for internal weak pull-up. 

RB7/T1OSI 13 I/O TTL/ST (2) Bi-directional I/O port/Timer1 oscillator input. Wake up from SLEEP on pin change. Can be 

software programmed for internal weak pull-up. 

VSS 5 P — Ground reference for logic and I/O pins. 

VDD 14 P — Positive supply for logic and I/O pins. 

Legend: 

O = output I/O = input/output P = power — = Not used 

I = Input ST = Schmitt Trigger input TTL = TTL input I/OD =input/open drain output 

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 

Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode. 

Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode. 

Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode. 

II.2. Architecture interne 

→ Architecture Harvard 

mémoire données 8 bits 

mémoire programme 14 bits 

SFRs en mémoire de données. 

ALU 8 bits 

1 registre de travail (W : working reg.) 8 bits 

flags du registre STATUS associés à ALU : 

C (Carry) 

DC (Digit Carry) 

Z (Zero) 

Pile sur 8 niveaux

16F628 PIC - 107 -

16F628 PIC - 108 - 

II.3. Organisation mémoire 

Mémoire programme 

2 k-mots de 14 bits (0000h-07FFh) 

cyclique ⇒ 0800h ≈ 0000h 

PC 13 bits 

Vecteur Reset en 0000h 

Vecteur d’iT en 0004h 

Pile 

Non implantée dans les plans mémoire 

Accessible par instructions spécifiques 

→ CALL, RETURN, RETFIE, RETLW 

8 niveaux (structure de buffer circulaire) 

Mémoire de données 

→ 4 banques de 128 octets (00h-7Fh) 

contient SFRs (32 premiers octets de chaque banque) 

Registres à usage général (RAM statique) : 

020h-07Fh 

0A0h-0FFh 

120h-14Fh 

170h-17Fh 

1F0h-1FFh 

Mémoire commune (16 octets en ad. hautes) dans chaque banque 

→ visible en 70h-7Fh

16F628 PIC - 109 - 

Plan mémoire :

16F628 PIC - 110 - 

SFRs 

STATUS 

→ registre d’état du processeur 

bit 7: 

bit 6-5: 

bit 4: 

bit 3: 

bit 2: 

bit 1: 

bit 0: 

IRP: Register Bank Select bit (used for indirect addressing) 

1 = Bank 2, 3 (100h - 1FFh) 

0 = Bank 0, 1 (00h - FFh) 

RP1:RP0: Register Bank Select bits (used for direct addressing) 

11 = Bank 3 (180h - 1FFh) 

10 = Bank 2 (100h - 17Fh) 

01 = Bank 1 (80h - FFh) 

00 = Bank 0 (00h - 7Fh) 

TO: Time-out bit 

1 = After power-up, CLRWDT instruction, or SLEEP instruction 

0 = A WDT time-out occurred 

PD: Power-down bit 

1 = After power-up or by the CLRWDT instruction 

0 = By execution of the SLEEP instruction 

Z: Zero bit 

1 = The result of an arithmetic or logic operation is zero 

0 = The result of an arithmetic or logic operation is not zero 

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for 

borrow the polarity is reversed) 

1 = A carry-out from the 4th low order bit of the result occurred 

0 = No carry-out from the 4th low order bit of the result 

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 

1 = A carry-out from the most significant bit of the result occurred 

0 = No carry-out from the most significant bit of the result occurred 

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of 

the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order 

bit of the source register.

16F628 PIC - 111 - 

OPTION 

→ registre de configuration 

bit 7: 

bit 6: 

bit 5: 

bit 4: 

bit 3: 

bit 2-0: 

RBPU: PORTB Pull-up Enable bit 

1 = PORTB pull-ups are disabled 

0 = PORTB pull-ups are enabled by individual port latch values 

INTEDG: Interrupt Edge Select bit 

1 = Interrupt on rising edge of RB0/INT pin 

0 = Interrupt on falling edge of RB0/INT pin 

T0CS: TMR0 Clock Source Select bit 

1 = Transition on RA4/T0CKI pin 

0 = Internal instruction cycle clock (CLKOUT) 

T0SE: TMR0 Source Edge Select bit 

1 = Increment on high-to-low transition on RA4/T0CKI pin 

0 = Increment on low-to-high transition on RA4/T0CKI pin 

PSA: Prescaler Assignment bit 

1 = Prescaler is assigned to the WDT 

0 = Prescaler is assigned to the Timer0 module 

PS2:PS0: Prescaler Rate Select bits 

Bit Value TMR0 Rate WDT Rate 

000 1 : 2 1 : 1 

001 1 : 4 1 : 2 

010 1 : 8 1 : 4 

011 1 : 16 1 : 8 

100 1 : 32 1 : 16 

101 1 : 64 1 : 32 

110 1 : 128 1 : 64 

111 1 : 256 1 : 128

16F628 PIC - 112 - 

INTCON 

→ Autorisation des interruptions 

bit 7: GIE: Global Interrupt Enable bit 

1 = Enables all un-masked interrupts 

0 = Disables all interrupts 

bit 6: PEIE: Peripheral Interrupt Enable bit 

1 = Enables all un-masked peripheral interrupts 

0 = Disables all peripheral interrupts 

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 

1 = Enables the TMR0 interrupt 

0 = Disables the TMR0 interrupt 

bit 4: INTE: RB0/INT External Interrupt Enable bit 

1 = Enables the RB0/INT external interrupt 

0 = Disables the RB0/INT external interrupt 

bit 3: RBIE: RB Port Change Interrupt Enable bit 

1 = Enables the RB port change interrupt 

0 = Disables the RB port change interrupt 

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 

1 = TMR0 register has overflowed (must be cleared in software) 

0 = TMR0 register did not overflow 

bit 1: INTF: RB0/INT External Interrupt Flag bit 

1 = The RB0/INT external interrupt occurred (must be cleared in software) 

0 = The RB0/INT external interrupt did not occur 

bit 0: RBIF: RB Port Change Interrupt Flag bit 

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in 

software) 

0 = None of the RB7:RB4 pins have changed state

16F628 PIC - 113 - 

PIE1 

→ Autorisation des interruptions 

bit 7: EEIE: EE Write Complete Interrupt Enable Bit 

1 = Enables the EE write complete interrupt 

0 = Disables the EE write complete interrupt 

bit 6: CMIE: Comparator Interrupt Enable bit 

1 = Enables the comparator interrupt 

0 = Disables the comparator interrupt 

bit 5: RCIE: USART Receive Interrupt Enable bit 

1 = Enables the USART receive interrupt 

0 = Disables the USART receive interrupt 

bit 4: TXIE: USART Transmit Interrupt Enable bit 

1 = Enables the USART transmit interrupt 

0 = Disables the USART transmit interrupt 

bit 3: Unimplemented: Read as ‘0’ 

bit 2: CCP1IE: CCP1 Interrupt Enable bit 

1 = Enables the CCP1 interrupt 

0 = Disables the CCP1 interrupt 

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 

1 = Enables the TMR2 to PR2 match interrupt 

0 = Disables the TMR2 to PR2 match interrupt 

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 

1 = Enables the TMR1 overflow interrupt 

0 = Disables the TMR1 overflow interrupt

16F628 PIC - 114 - 

PIR1 

→ Registre d’indicateurs d’interruptions reçues 

bit 7: EEIF: EEPROM Write Operation Interrupt Flag bit 

1 = The write operation completed (must be cleared in software) 

0 = The write operation has not completed or has not been started 

bit 6: CMIF: Comparator Interrupt Flag bit 

1 = Comparator input has changed 

0 = Comparator input has not changed 

bit 5: RCIF: USART Receive Interrupt Flag bit 

1 = The USART receive buffer is full 

0 = The USART receive buffer is empty 

bit 4: TXIF: USART Transmit Interrupt Flag bit 

1 = The USART transmit buffer is empty 

0 = The USART transmit buffer is full 

bit 3: Unimplemented: Read as ‘0’ 

bit 2: CCP1IF: CCP1 Interrupt Flag bit 

Capture Mode 

1 = A TMR1 register capture occurred (must be cleared in software) 

0 = No TMR1 register capture occurred 

Compare Mode 

1 = A TMR1 register compare match occurred (must be cleared in software) 

0 = No TMR1 register compare match occurred 

PWM Mode 

Unused in this mode 

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 

1 = TMR2 to PR2 match occurred (must be cleared in software) 

0 = No TMR2 to PR2 match occurred 

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 

1 = TMR1 register overflowed (must be cleared in software) 

0= TMR1 register did not overflow

16F628 PIC - 115 - 

PCON 

→ registre de configuration 

bit 7-4,2:Unimplemented: Read as '0' 

bit 3: OSCF: INTRC/ER oscillator speed 

1 = 4 MHz typical (1) 

0 = 37 KHz typical 

bit 1: POR: Power-on Reset Status bit 

1 = No Power-on Reset occurred 

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset 

occurs) 

bit 0: BOD: Brown-out Detect Status bit 

1 = No Brown-out Reset occurred 

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset 

occurs) 

Note 1: When in ER oscillator mode, setting OSCF = 1 will cause the oscillator speed to change to the 

speed specified by the external resistor. 

PCL et PCLATH 

→ constitution de PC (13 bits)

16F628 PIC - 116 - 

INDF et FSR 

→ Adressage indirect 

FSR contient l’adresse de la donnée 

L’opération de lecture ou d’écriture sur INDF porte en réalité sur la donnée pointée par FSR. 

Exemple : effacement de la mémoire 20h à 2Fh 

movlw 0x20 ;initialize pointer 

movwf FSR ;to RAM 

NEXT: clrf INDF ;clear INDF register 

incf FSR ;inc pointer 

btfss FSR,4 ;all done? 

goto NEXT ;no clear next 

;yes continue 

CONTINUE:

16F628 PIC - 117 - 

Mémoire EEPROM 

→ Permet de sauvegarder des données (mémoire non volatile) 

→ Écritures/lectures non « instantanées » 

EEDATA : 

→ Contient la donnée lue ou à écrire 

EEADR : 

→Indique l’adresse de la donnée 

bit 7 Unimplemented Address: Must be set to '0' 

bit 6:0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation 

EECON1 : 

→ Indique le type d’opération à réaliser. 

bit 7:4 Unimplemented: Read as '0' 

bit 3 WRERR: EEPROM Error Flag bit 

1 = A write operation is prematurely terminated 

(any MCLR reset, any WDT reset during normal operation or BOD detect) 

0 = The write operation completed 

bit 2 WREN: EEPROM Write Enable bit 

1 = Allows write cycles 

0 = Inhibits write to the data EEPROM 

bit 1 WR: Write Control bit 

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. 

The WR bit can only be set (not cleared) in software. 

0 = Write cycle to the data EEPROM is complete 

bit 0 RD: Read Control bit 

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. 

The RD bit can only be set (not cleared) in software). 

0 = Does not initiate an EEPROM read

16F628 PIC - 118 - 

II.4. Fonctionnements spéciaux 

Mot de configuration 

→ Accessible uniquement en phase de programmation (électrique)

16F628 PIC - 119 - 

II.5. Oscillateur 

Oscillateur à quartz (ou résonateurs céramiques) 

Horloge externe 

Oscillateur externe 

→ Il est préférable d’utiliser un oscillateur intégré (plus stable). 

Résistance externe 

→ Pour applications ne nécessitant pas une grande précision temporelle. 

La résistance doit être comprise entre 38k et 1MΩ 

Fournit une horloge entre 10kHz et 8MHz 

RC interne 

Fournit en interne un oscillateur à 4MHz (5V / 25°C) 

II.6. Démarrage du système 

6 possibilités au démarrage du système : 

• Power on reset (POR) 

→ mise sous tension du système 

• MCLR activé pendant fonctionnement normal 

• MCLR activé pendant mode SLEEP 

• Watchdog pendant fonctionnement normal 

• Watchdog pendant le mode SLEEP 

• Chute de la tension d’alimentation (Brown-Out Detect) 

→ quand Vcc tombe en dessous de 4V.

16F628 PIC - 120 - 

Configurations possibles (flags de STATUS & PCON) 

POR BOD TO PD 

0 x 1 1 Power-on-reset 

1 0 x x Brown-out Detect 

1 1 0 u WDT Reset 

1 1 0 0 WDT Wake-up 

1 1 u u MCLR reset during normal operation 

1 1 1 0 MCLR reset during SLEEP 

Legend: u = unchanged, x = unknown 

II.7. Interruptions 

Sources d’interruptions : 

Interruption externe RB0/INT 

TMR0 overflow 

TMR1 overflow 

TMR2 match 

Changement sur PortB (RB7 :RB4) 

Comparateur 

USART 

CCP 

Masquages individuels et masquage global dans INTCON. 

Quand iT demandée : 

• GIE (Global Interrupt Enable) mis à 0 (interdit autres iT) 

• Adresse de retour empilée 

• PC chargé avec 0004h 

• … sauvegarder W et STATUS (pas dans la pile !) 

• … vérification de la source d’iT 

• … traitement de l’iT 

• … acquittement de l’iT par remise à 0 des flags d’iT 

• RETFIE → termine la routine d’iT (et remet GIE à 1). 

Sauvegarde de W et STATUS en RAM : 

MOVWF W_TEMP 

;copy W to temp register, could be in either bank 

SWAPF STATUS,W 

;swap status to be saved into W 

BCF STATUS,RP0 

;change to bank 0 regardless of current bank 

MOVWF ST_TEMP 

;save status to bank 0 register 

: 

: (ISR) 

: 

SWAPF ST_TEMP,W ;swap ST_TEMP register into W, 

;sets bank to original state 

MOVWF STATUS 

;move W into STATUS register 

SWAPF W_TEMP,F 

;swap W_TEMP 

SWAPF W_TEMP,W 

;swap W_TEMP into W 

II.8. Watchdog 

→ compteur indépendant. 

Durée ≈ 18ms sans prédiviseur d’horloge (jusqu’à 2,3s avec) 

Activé par WDTE du mot de configuration 

Fonctionne même si horloge arrêtée (sur OSC1, OSC2) par SLEEP. 

En mode normal → déclenchement d’un RESET 

En mode SLEEP → réveil du µP → retour au fonctionnement normal.

16F628 PIC - 121 - 

CLRWDT et SLEEP initialisent le watchdog 

II.9. Mode Power-down 

→ atteint par l’instruction SLEEP 

→ arrête le driver de l’oscillateur (arrêt de l’horloge) 

Réveil par : 

• MCLR → Réinitialisation du système 

• Watchdog 

• Interruption sur RB0/INT ou RB change ou comparateur 

Poursuite du 

programme 

II.10. Programmation électrique 

Programmation de type série 

- horloge 

- donnée 

- tension de programmation 

- alimentations (5V, GND) 

2 possibilités : 

avec tension de programmation 

RB6 & RB7 maintenus à 0 pendant que Vpp passe de 0 à VIHH (V DD +3,5 à 13,5V) 

en basse tension (5V) 

bit LVP du mot de configuration mis à 1. 

Mode programmation atteint quand RB4=1 (interdit utilisation de RB4 en E/S) 

LVP peut être mis à 1 en mode « haute tension » (ce mode est toujours disponible).

16F628 PIC - 122 - 

II.11. Programmation logicielle 

Ecriture de programmes 

Instructions sur octets 

'f' : registre (file register), de 0 à 7Fh 

'd' : destination 

si d=0 → résultat dans W 

si d=1 → résultat dans 'f' 

Exemples : 

CLRW 

0 → W 

DECF CNT,1 CNT-1 → CNT 

DECF CNT,0 CNT-1 → W 

ENCORE DECFSZ REG,1 décrémente REG ; SKIP * si Zéro 

GOTO ENCORE brancher à ENCORE si REG ≠ 0 

SUITE 

f défini = 1 

SWAP RG1,f si RG1=F4h ⇒ RG1=4Fh 

SUBWF AB,W AB-W → W ; C=1 si résultat ≥ 0 

W défini = 0 

(*) : n'exécute pas l'instruction suivante. 

Instructions sur bits 

'b' : numéro du bit affecté par l'opération (0 à 7) 

'f' : registre 

Exemples : 

BCF REG,3 met à 0 le bit 3 de REG 

BTFSC CNT,7 test du bit 7 de CNT ; SKIP si = 0 

Opérations littérales et de contrôle 

'k' : constante de 8 ou 11 bits, ou valeur littérale 

Exemples : 

ADDLW 23 

W+23 → W ; k sur 8 bits 

CALL TOTO appel du sous pgm TOTO ; k sur 11 bits 

GOTO SUITE 

MOVLW 0x03 

03h → W 

CLRWDT 

remise à 0 du Watchdog 

SLEEP 

mise en veille (réveil par RESET, iT ou WDT) 

RETLW 0x12 

⇔ W=12h ; RETURN 

Utilisation de RETLW (lecture d'une donnée en mémoire programme) : 

MOVLW 5 

CALL TABLE 

……….. 

TABLE 

ADDWF PC 




………..

16F628 PIC - 123 - 

Jeu d’instructions 

Mnemonic Operands Description Cycles 

MSb 

14-Bit Opcode 

LSb 

Status 

Affected 

Notes 

BYTE-ORIENTED FILE REGISTER OPERATIONS 

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 

ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 

CLRF f Clear f 1 00 0001 lfff ffff Z 2 

CLRW - Clear W 1 00 0001 0xxx xxxx Z 

COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 

DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 

DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 

INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 

IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 

MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 

MOVWF f Move W to f 1 00 0000 lfff ffff 

NOP - No Operation 1 00 0000 0xx0 0000 

RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 

RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 

SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 

SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 

XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 

BIT-ORIENTED FILE REGISTER OPERATIONS 

BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 

BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 

BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 

LITERAL AND CONTROL OPERATIONS 

ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z 

ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z 

CALL k Call subroutine 2 10 0kkk kkkk kkkk 

CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD 

GOTO k Go to address 2 10 1kkk kkkk kkkk 

IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z 

MOVLW k Move literal to W 1 11 00xx kkkk kkkk 

RETFIE - Return from interrupt 2 00 0000 0000 1001 

RETLW k Return with literal in W 2 11 01xx kkkk kkkk 

RETURN - Return from Subroutine 2 00 0000 0000 1000 

SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD 

SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z 

XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z 

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. 

For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 

Note 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 

Note 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

Table des matières - 124 - 

CHRONOGRAMMES DU 6809 (MOTOROLA) .............................................................................................. 2 

HN58S65AI (EEPROM)....................................................................................................................................... 4 

HM65764 (RAM STATIQUE) ............................................................................................................................. 5 

TL16C450 (COMMUNICATION SERIE) ......................................................................................................... 6 

BROCHAGE, CHRONOGRAMMES.......................................................................................................................... 6 

DESCRIPTION DES SIGNAUX................................................................................................................................. 6 

AUTRES CIRCUITS LOGIQUES...................................................................................................................... 8 

DECODEURS DEMULTIPLEXEURS......................................................................................................................... 8 

74138............................................................................................................................................................. 8 

74139............................................................................................................................................................. 9 

BUFFERS ............................................................................................................................................................. 9 

74244............................................................................................................................................................. 9 

74245........................................................................................................................................................... 10 

LATCHES........................................................................................................................................................... 10 

74373........................................................................................................................................................... 10 

C167CR.............................................................................................................................................................- 12 - 

PRESENTATION ...........................................................................................................................................- 13 - 

FAMILLE C166 .............................................................................................................................................. - 13 - 

VERSIONS DU C167....................................................................................................................................... - 13 - 

ARCHITECTURE INTERNE............................................................................................................................... - 14 - 

ORGANISATION MEMOIRE......................................................................................................................- 16 - 

RAM INTERNE ET SFR.................................................................................................................................. - 17 - 

MEMOIRE XRAM ......................................................................................................................................... - 17 - 

REGISTRES A USAGE GENERAL ...................................................................................................................... - 18 - 

MEMOIRE EXTERNE....................................................................................................................................... - 18 - 

CPU ..................................................................................................................................................................- 19 - 

PIPELINE ....................................................................................................................................................... - 20 - 

PILE SYSTEME ............................................................................................................................................... - 21 - 

SFRS (SPECIAL FUNCTION REGISTERS)..............................................................................................- 22 - 

INTERRUPTIONS .........................................................................................................................................- 27 - 

SOURCES ET VECTEURS D'INTERRUPTION ...................................................................................................... - 27 - 

REGISTRES DE CONTROLE DES INTERRUPTIONS............................................................................................. - 29 - 

GESTION DES PRIORITES................................................................................................................................- 29 - 

TRAPS ........................................................................................................................................................... - 30 - 

PORTS PARALLELES..................................................................................................................................- 31 - 

FONCTIONS ALTERNEES ................................................................................................................................- 31 - 

REGISTRES ASSOCIES AU PORT 0 ................................................................................................................... - 32 - 









TIMERS...........................................................................................................................................................- 36 - 

GPT1 ............................................................................................................................................................ - 36 - 

GPT2 ............................................................................................................................................................ - 39 - 

UNITES CAPTURE/COMPARE..................................................................................................................- 41 - 

PWM ................................................................................................................................................................- 44 -


CONVERTISSEUR A/N ................................................................................................................................- 47 - 

PORT SERIE ..................................................................................................................................................- 49 - 

INTERFACE CAN .........................................................................................................................................- 50 - 

SYSTEME PEC ..............................................................................................................................................- 52 - 

PROGRAMMATION.....................................................................................................................................- 53 - 

INSTRUCTIONS .............................................................................................................................................. - 53 - 

ADRESSAGES................................................................................................................................................. - 58 - 

BUS EXTERNE ..............................................................................................................................................- 60 - 

LISTE DES REGISTRES ..............................................................................................................................- 65 - 

COMPILATEUR TASKING C166 ...............................................................................................................- 69 - 

TYPES DE DONNEES....................................................................................................................................... - 69 - 

TAILLE DES DONNEES.................................................................................................................................... - 69 - 

IMPLEMENTATION ET EXTENSIONS................................................................................................................ - 69 - 

Fichier de définition des registres ...........................................................................................................- 69 - 

Modèles de mémoire................................................................................................................................- 69 - 

_bita.........................................................................................................................................................- 70 - 

_at(adresse).............................................................................................................................................- 70 - 

_atbit( name, offset )................................................................................................................................- 70 - 

_inline......................................................................................................................................................- 70 - 

_interrupt.................................................................................................................................................- 70 - 

#pragma asm ...........................................................................................................................................- 71 - 

Registres utilisés......................................................................................................................................- 71 - 

Fonctions intrinsèques.............................................................................................................................- 71 - 

Portabilité................................................................................................................................................- 71 - 

CODE GENERE ............................................................................................................................................... - 72 - 

Observations générales ...........................................................................................................................- 72 - 

Utilisation de constantes .........................................................................................................................- 73 - 

Déclarations de données .........................................................................................................................- 74 - 

Elimination du code superflu...................................................................................................................- 75 - 

Utilisation de macros ..............................................................................................................................- 76 - 

Utilisation d'unions .................................................................................................................................- 77 - 

Fonctions _inline.....................................................................................................................................- 78 - 

Opérations : Calcul de a*b/c...................................................................................................................- 80 - 

Interruptions............................................................................................................................................- 81 - 

Définition des constantes - Bilan.............................................................................................................- 82 - 

STARTER KIT STK16X500..........................................................................................................................- 83 - 

MINIMODULE TQM167C............................................................................................................................- 88 - 

Microcontroller SAB-C167-LM / SAB-167CR-LM..................................................................................- 89 - 

Memory....................................................................................................................................................- 89 - 

Reset-Logic..............................................................................................................................................- 89 - 

Interface...................................................................................................................................................- 89 - 

Internal LED............................................................................................................................................- 89 - 

Model No. and Order Code .....................................................................................................................- 90 - 

Memory Management..............................................................................................................................- 90 - 

Programming of the Chip Select lines.....................................................................................................- 91 - 

Programming the XREG register ............................................................................................................- 92 - 

Internal bootstrap loader.........................................................................................................................- 93 - 

Power fail supervisor ..............................................................................................................................- 94 - 

Technical Data ........................................................................................................................................- 94 - 

Connecteurs.............................................................................................................................................- 95 - 

ENVIRONNEMENT TASKING...................................................................................................................- 96 - 

APPLICATIONS ............................................................................................................................................- 97 - 

CHENILLARD................................................................................................................................................. - 97 - 

TEMPORISATIONS.......................................................................................................................................... - 97 -


CONVERTISSEUR ANALOGIQUE ..................................................................................................................... - 97 - 

SIGNAL PWM ............................................................................................................................................... - 97 - 

GENERATION ET MESURE DE SIGNAUX .......................................................................................................... - 97 - 

LIMITEUR D'ACCELERATION POUR LA COMMANDE DE MOTEUR..................................................................... - 98 - 

MICROCONTROLEURS PIC.......................................................................................................................... 99 

I. PIC 16C73A .................................................................................................................................................. 99 

I.1. Caractéristiques générales.................................................................................................................... 99 

I.2. Architecture........................................................................................................................................... 99 

I.3. Organisation mémoire........................................................................................................................... 99 

I.4. Registres du processeur ...................................................................................................................... 101 

I.5. Programmation ................................................................................................................................... 102 

II. PIC 16F628 ................................................................................................................................................ 105 

II.1. Présentation générale ........................................................................................................................ 105 

II.2. Architecture interne ........................................................................................................................... 106 

II.3. Organisation mémoire ....................................................................................................................... 108 

EEDATA :.................................................................................................................................................. 117 

EEADR :.................................................................................................................................................... 117 

EECON1 :.................................................................................................................................................. 117 

II.4. Fonctionnements spéciaux ................................................................................................................. 118 

II.5. Oscillateur ......................................................................................................................................... 119 

II.6. Démarrage du système....................................................................................................................... 119 

II.7. Interruptions ...................................................................................................................................... 120 

II.8. Watchdog ........................................................................................................................................... 120 

II.9. Mode Power-down............................................................................................................................. 121 

II.10. Programmation électrique ............................................................................................................... 121 

II.11. Programmation logicielle ................................................................................................................ 122 

Jeu d’instructions ...................................................................................................................................... 123

IUP GEII - Abcelectronique

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