Embedded EEPROM Specification - picmg

5.1.2.13 PCI Express Lane Descriptor Data Structure(LaneMap)
Lane numbers 0 through 31 refer to the 32 possible COM Express® lanes. Each COM Express®
connector PCI Express lane is allocated four bits to describe how the lanes are grouped on the Carrier
Board to form PCI Express links.
The 32 PCIe lanes are described in an array of 16 bytes, each lane using 4 bits. A lane is described by
three bits indicating the width of the link it is part of, and a single bit defining the PCIe Generation of
the link. This definition implies that the start lane of a link must be aligned at a boundary which is an
integral multiple of the width of the link it is part of, e.g. a x4link can start only at lane no.
0,4,8,16,20,24, and 28.
A link (along with its width and starting lane) can be decoded by inspecting the single Mapping Nibble
of a lane which is part of the link. Figure "C_SAMPLE 3: Decode PCIe Link Width & Start Lane" on
page 29 is showing this for lane 15.".
Table 5-8: PCI Express Lane Descriptor Nibble Descriptor
Bits Description Values Meaning
0 - 2 Link Width/Alignment 0 Not Implemented
1 x1 Link Width
2 x2 Link Width
3 x4 Link Width
4 x8 Link Width
5 x16 Link Width
6 x32 Link Width
7 Reserved
3 Reserved 0 Reserved.
Table 5-9: PCI Express Valid Starting Lane Configurations
Link Width
Valid Starting Lane
x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,...
x2 0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30
x4 0,4,8,12,16,20,24,28
x8 0,8,16,24
x16 0.16
x32 0
PICMG® EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 28 of 84