1 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
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Industry Trends
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

“ Moore's Law” Impact on Micro-Computers
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Up to 2B Transistors per chip in 2008.
Serial data links operating at 10 Gbits/sec.
Increased reuse of logic IP, i.e. designs
and cores.
0.045 m
YEAR
2010
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Moore's Law and More
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Improvement Trends for VLSI SoCs Enabled by
Geometrical and Equivalent Scaling
TRENDS
1. Higher Integration level -> exponentially increased
number of components/transistors per chip.
2. Performance Scaling -> combination of Geometrical and
Equivalent Scaling.
3. System implementation -> SoC + increased use of SiP
4. Higher Speed -> CPU clock rate at multiple GHz.
5. Increased Compactness -> Smaller and lighter weight
electronic products
6. Lower Power -> Increased laptop, cell phone and PDA
battery life.
7. Lower Cost -> Decreasing cost per function.
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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DPE -> Digital Processing Engine
From http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf
Since digital functions will be implemented and realized mainly by software
and high processing power is required, high performance consumer
stationary SOCs will have many data processing engines ( DPEs).
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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From http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Digital CMOS Basics
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Classification of Digital CMOS Circuits
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
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Ideal nMOS and pMOS Characteristics
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High Impedance or High Z
High Impedance or High Z
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Complementary CMOS Switch
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Ideal CMOS Inverter
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Inverter Truth Table
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Two-Input CMOS NAND Gate
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DeMorgan's Theorem
A⋅B= AB
A B
F = A⋅B
A⋅B
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Two-Input CMOS NOR Gate
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DeMorgan's Theorem
AB= A⋅B
A⋅B
AB
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Constructing Compound CMOS Gates
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F = A⋅BC⋅D
F = A⋅BC⋅D
N-Half Circuit
F
F = AB⋅C D
P-Half Circuit
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
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F = A⋅BC⋅D
Combing the N-Half
and P-Half Circuits
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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output=A⋅sB⋅s
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Some VLSI Fundamentals
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

VLSI Hierarchical Representations
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Typical Digital VLSI Design Abstractions
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Consistent Abstractions in Three Domains
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Application Specs.
Architecture,
e.g. RISC Processor
Architectural
Abstraction
Level
Chip, SoC, SiP
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Goal of All VLSI Design Enterprises
Convert System Specs into an SOC DESIGN in MINIMUM
TIME and with MAXIMUM LIKLIHOOD that the Design
will PEFORM AS SPECIFIED when fabricated.
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Basic VLSI Chip Cost Model
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

VLSI Design Cycle
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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Illustrative Circuit Design Example
Design a One-Bit Adder Circuit using 0.8
! 8µ m twin-well CMOS Technology. technology. The
design specifications are:
1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns
2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns
3. Circuit Die Area: ≤ 1500 m 2
4. Dynamic Power Dissipation (@ V DD
= 5 V and f max
= 20 MHz): ≤ 1 mW
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Bit-Sliced Data Path
Control
Bit N
Data IN
Register ADDER Shifter Multiplier
Data OUT
Bit 0
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Illustrative Circuit Design Example
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Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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A
B
Two-Input Exclusive OR Gate
A
B
F = A +
XOR
output
F = A +
B = A⋅BA⋅B
B
Three-Input Exclusive OR Gate
XOR
C
F + +
2
= A B C =
F 1
XOR output + + F 2
= A B C
In Out = F
A B A + B
0 0 0
0 1 1
1 0 1
1 1 0
= A⋅B⋅CA⋅B⋅C A⋅AA⋅BA⋅BB⋅B⋅C
In F 1
In Out = F 2
A B A + B C A + B + C
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
AB⋅ AB
F 1
⋅CF 1
⋅C= A⋅BA⋅B⋅C A⋅BA⋅B⋅C
0 0
= A⋅B⋅C A⋅B⋅C A⋅B⋅CA⋅B⋅C
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Gate Level Schematic of One-Bit Full Adder Circuit
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AB⋅CA⋅B
ABC⋅CARRYOUT
A⋅B⋅C ABC ⋅CARRYOUT
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Show
SUMOUT=A⋅B⋅C ABC ⋅CARRYOUT = A + B + C
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CARRYOUT= AB⋅C A⋅B= A⋅CB⋅CA⋅B
Using DeMorgan's Theorem
CARRYOUT= A⋅CB⋅C A⋅B= A⋅C⋅B⋅C⋅ A⋅B
= A⋅C⋅ B⋅C ⋅ A⋅B= AC⋅ BC⋅ AB
= A⋅BA⋅CC⋅BC⋅ AB
= A⋅BA⋅C A⋅B⋅CA⋅C A⋅B A⋅B⋅CB⋅CB⋅C
= A⋅B A⋅C A⋅B⋅CB⋅C
SUMOUT=A⋅B⋅C ABC ⋅CARRYOUT
= A⋅B⋅C ABC ⋅ A⋅B A⋅CA⋅B⋅CB⋅C
= A⋅B⋅CA⋅B⋅CA⋅B⋅C A⋅B⋅C
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Transistor Level Schematic of One-Bit Full Adder Circuit
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COUT
AB⋅C A⋅B
COUT
SUMOUT
ABC⋅COUT
A⋅B⋅C ABC ⋅COUT
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Initial Layout of One-Bit Full Adder Circuit
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N1
N2
COUT
SUMOUT
N1
N1
N2
N2
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Initial Layout of One-Bit Full Adder Circuit
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≤ 1500 m 2
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

Simulated Performance of One-Bit Full Adder Circuit
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Spec NOT
met.
Kenneth R. Laker, University of Pennsylvania, updated 15Jan09