The International Technology Roadmap for Semiconductors (ESH ...
The International Technology Roadmap for Semiconductors (ESH ...
The International Technology Roadmap for Semiconductors (ESH ...
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<strong>The</strong> <strong>International</strong> <strong>Technology</strong><br />
<strong>Roadmap</strong> <strong>for</strong> <strong>Semiconductors</strong><br />
(<strong>ESH</strong> THRUST)<br />
2000<br />
Jim Jewett<br />
Intel Corporation<br />
Arlington, VA; April 2000
<strong>The</strong> ITRS is a document<br />
which identifies<br />
technology needs and<br />
possible solutions<br />
Arlington, VA; April 2000
From NTRS to ITRS<br />
• <strong>The</strong> SIA NTRS document has been recognized<br />
internationally as a useful document<br />
• Semiconductor Industry has become global<br />
• Inputs into NTRS limited to the USA companies<br />
• Broader participation would enrich the data and<br />
give better guidance to global suppliers and<br />
researchers<br />
Arlington, VA; April 2000
SIA <strong>Roadmap</strong> Acceleration<br />
500<br />
95 97 99 01 04 07 10<br />
13<br />
350<br />
1994<br />
Minimum Feature Size (nm)<br />
250<br />
180<br />
130<br />
100<br />
70<br />
Best Case<br />
Opportunity<br />
1997<br />
1998<br />
50<br />
35<br />
25<br />
IRC/ITWG<br />
Agreement July,1999<br />
MPU Gate<br />
DRAM Half Pitch<br />
95 97 99 01 04 07 10<br />
13<br />
11<br />
Arlington, VA; April 2000
More Aggressive Goal<br />
vs.<br />
Most Achievable Goal<br />
Arlington, VA; April 2000
1999 ITRS<br />
Provides:<br />
• Targets <strong>for</strong> equipment/material and<br />
software suppliers<br />
• Targets <strong>for</strong> researchers<br />
• A common reference <strong>for</strong> the<br />
semiconductor industry<br />
Arlington, VA; April 2000
Presumes That Driving <strong>ESH</strong><br />
Solution During <strong>Technology</strong><br />
Development Is <strong>The</strong> Right<br />
Thing To Do.<br />
Arlington, VA; April 2000
EHS:<strong>Technology</strong> Engagement Model<br />
Here is where we need<br />
to operate more often<br />
Here is where we<br />
operate today<br />
Optimal Integration<br />
Process-specific<br />
environmental<br />
impacts unknown<br />
Company Research ... Process Development<br />
Process too close to<br />
manufacturing <strong>for</strong><br />
major change<br />
External Research<br />
Supplier R&D<br />
Equip. Selection<br />
Mfg. Ramp<br />
0 2 4 6 8 10+<br />
Concept Development α β<br />
Commercialization Phases<br />
Years<br />
Integration<br />
Demonstration<br />
Ramp to<br />
High Vol.<br />
Mfg.<br />
Arlington, VA; April 2000
<strong>Technology</strong> Driven <strong>ESH</strong><br />
Objectives<br />
vs.<br />
“Regulatory Driven <strong>ESH</strong><br />
Objectives<br />
Arlington, VA; April 2000
Semiconductor <strong>Technology</strong> Environmental "<strong>Roadmap</strong>" Rev. 0 12/98<br />
<strong>Technology</strong> Generation 8" / 0.18um 8" / 0.15um 12" / 0.13um 12" / 0.10um 12" / 0.07um 12" / 0.05um<br />
Year 1999 2001 2003 2006 2009 2012<br />
Increase Product Speed<br />
1. Technical Feature<br />
(Technical Decription) -<br />
Potential Environmental<br />
Impact Area(s)<br />
1. Interconnect (Cu<br />
metal) - PFCs, HAPs,<br />
Waste, Water, Slurry<br />
Use<br />
1. Metal Bumps<br />
(Potential Lead ban) -<br />
Waste, Water, Energy<br />
1. Metal Bumps<br />
(Potential Lead ban) -<br />
Waste, Water, Energy<br />
1. Gate Dielectric<br />
(Oxynitride/Silicon<br />
Nitride) - PFCs, HAPs,<br />
VOCs, Energy<br />
1. Gate Dielectric<br />
(alternaitve High k<br />
dielectric) - PFCs, HAPs,<br />
VOCs, Energy<br />
Increase Power<br />
Dissipation Capablility,<br />
Decrease in Power<br />
Consumption<br />
2. Technical Feature<br />
(Technical Decription) -<br />
Potential Environmental<br />
Impact Area(s)<br />
2. Gate Electrode<br />
(Poly/Silicide Gates) -<br />
PFCs, HAPs, VOCs,<br />
Energy, Slurry Use<br />
2. Gate Electrode<br />
(Metal Gates) - PFCs,<br />
HAPs, VOCs, Energy,<br />
Waste, Water, Slurry<br />
Use<br />
1. Interconnect<br />
(Advanced <strong>Technology</strong>) -<br />
???<br />
Increase Product<br />
Density/Capacity<br />
Decrease Electrical<br />
Defect Density<br />
1. Resist Development<br />
(193 nm resist)- VOCs,<br />
Water<br />
1. Resist Development<br />
(Post Optical) - VOCs,<br />
Water, Energy<br />
2. Lithography Type<br />
(Post Optical) - Energy,<br />
VOCs<br />
Minimize Signal Loss<br />
Increase Wafer Size (300<br />
mm)<br />
Decrease Final Cost<br />
1. Low K ILD (SiOF) -<br />
PFCs, HAPs<br />
1. Low K ILD (CxFy) -<br />
PFCs, HAPs<br />
2. Low K ILD (Spin-on<br />
Polymer) - VOCs, PFCs,<br />
HAPs, Water, Waste,<br />
Slurry Use<br />
1. Drain Extension &<br />
Contact Doping (New<br />
Process) - ???<br />
n/a n/a 1. FOUP (cleaning) -<br />
Surfactants<br />
2. Larger Tool Set<br />
(consumption) - PFCs,<br />
HAPs, VOCs, Water,<br />
Waste, Energy<br />
1. Drain Extension &<br />
Contact Doping (New<br />
Process) - ???<br />
Arlington, VA; April 2000
Five Global Challenges<br />
• Chemicals, Materials, and Equipment<br />
Management<br />
• Climate Change Mitigation<br />
• Workplace Protection<br />
• Resource Conservation<br />
• <strong>ESH</strong> Design and Measurement Methods<br />
Arlington, VA; April 2000
Arlington, VA; April 2000
Factory Int.<br />
<strong>ESH</strong> Crosscut<br />
Text &Table<br />
Front End<br />
Processes<br />
<strong>ESH</strong> Crosscut<br />
Text & Table<br />
Lithography<br />
<strong>ESH</strong> Crosscut<br />
Text & Table<br />
Interconnect<br />
<strong>ESH</strong> Crosscut<br />
Text & Table<br />
Assmbly &<br />
Pkg<br />
<strong>ESH</strong> Crosscut<br />
Text & Table<br />
<strong>ESH</strong> <strong>Roadmap</strong> Format<br />
Scope & Diff. Challenges<br />
Tech Reqmts<br />
Interconnect<br />
Lithography<br />
Potential Sols<br />
Front-End Processing<br />
Assembly & Packaging<br />
Factory Integration<br />
Links<br />
For additional<br />
in<strong>for</strong>mation to<br />
further explain<br />
data<br />
<strong>ESH</strong> <strong>Technology</strong> Requirements<br />
<strong>ESH</strong> Potential Solutions<br />
Difficult<br />
Challenges<br />
Chem, Mtls & Eq Mgmt<br />
Interconnect<br />
Years/Nodes<br />
Chem, Mtls & Eq Mgmt<br />
Interconnect<br />
Years/Nodes<br />
FEP<br />
FEP<br />
Arlington, VA; April 2000
2000/2001 ITRS Preliminary<br />
Schedule<br />
2000 ITRS Update<br />
• Kick off 2000 ITRS Update on Dec 1st, 1999<br />
• 3 major ITRS meetings: Europe in April, US in<br />
July, Japan in December<br />
2001 ITRS<br />
• December 2000. Kick off In Japan<br />
• Presentation of draft in conjunction with Semicon<br />
West<br />
• December 2001. Publication and Presentation<br />
Arlington, VA; April 2000
Backup Material<br />
Arlington, VA; April 2000
<strong>ESH</strong> <strong>International</strong> <strong>Technology</strong> Working<br />
Group (ITWG) Members<br />
Semiconductor Industry<br />
Association (SIA)<br />
Jim Jewett, Intel<br />
Larry Novak, Radian<br />
Electronic Industries<br />
Association of Japan (EIAJ)<br />
Osamu Anzai, Fujitsu<br />
Jun-ichi Aoyama, Sony<br />
Korea Semiconductor<br />
Industry Association (KSIA)<br />
C.H. Cho, LG Semicon<br />
European Electronic<br />
Component Association (EECA)<br />
Francesca Illuzzi, STM<br />
Leo Klerks, Philips<br />
Wolfgang Bloch, Infineon<br />
Taiwan Semiconductor<br />
Industry Association (TSIA)<br />
Eddy Liu, TSMC<br />
Jung-Sheng Hsiue, TSMC<br />
Abel C.F. Hsu, UMC<br />
Arlington, VA; April 2000
New Chemicals and Materials<br />
Technical Drivers<br />
Interconnect<br />
• Lo-K<br />
• Copper<br />
• Advanced metalization<br />
• Hi-K<br />
Lithography<br />
• Photoresists<br />
• Thinners<br />
• Developers<br />
• Rinses<br />
• Strippers<br />
Front-End Processes<br />
• Precursors <strong>for</strong> Hi-K and<br />
electrode films<br />
• Metal-containing precursors<br />
• Hydride-based dopant precursors<br />
• Cleaning processes<br />
Assembly and Packaging<br />
• Lead alternatives<br />
• Flame retardants<br />
• Solvents<br />
Arlington, VA; April 2000
1998/99 ITRS Working Groups<br />
<strong>International</strong><br />
<strong>Technology</strong><br />
Working Groups<br />
(ITWG)<br />
Design<br />
Environment<br />
Safety &<br />
Health<br />
<strong>International</strong> Crosscut <strong>Technology</strong><br />
Working Group (ICCT WG)<br />
Metrology<br />
Defect<br />
Reduction<br />
Modeling &<br />
Simulation<br />
Test<br />
Front End Processes<br />
Interconnect<br />
Lithography<br />
Process Integration<br />
Assembly & Packaging<br />
Factory Integration<br />
Arlington, VA; April 2000
<strong>Technology</strong> Flow<br />
<strong>Technology</strong> Needs<br />
Potential Solutions<br />
Consortia<br />
Researchers<br />
Suppliers<br />
Detailed<br />
Solutions<br />
Implementation<br />
Suppliers<br />
Manufacturers<br />
Arlington, VA; April 2000
1999 <strong>Technology</strong> Nodes and Timing<br />
Short Term Years<br />
Year<br />
of<br />
Introduction<br />
1999 2000 2001 2002 2003 2004 2005<br />
180 130 100<br />
nm nm nm<br />
Dram 1/2 Pitch (nm) 180 165 150 130 120 110 100<br />
MPU Gate Length (nm) 140 120 100 85 89 70 65<br />
Long Term Years<br />
Year<br />
of<br />
Introduction<br />
2008 2011 2014<br />
70 50 35<br />
nm nm nm<br />
Dram 1/2 Pitch (nm) 70 50 35<br />
MPU Gate Length (nm) 45 32 22<br />
Arlington, VA; April 2000
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