Chip Design Trends - Synopsys.com

From the publishers of:
Chip Design Trends
Data, Analysis, and Benchmarking on SOC Design
Vol. 1, No. 5 March 2007
Executive Summary
• Embedded memories
show growth (pg 2)
• Is the core meltdown
just a false alarm?
(pg 7)
• Synopsys prepares
for future growth in IP
segment (pg 9)
• Design interest to peak
in March, while power
ranges rise! (pg 10)
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In This Issue
2 ■ Analysis and Trends
7 ■ Behind the Numbers
9 ■ IP Trends
10 ■ Performance, Power
and Area
Embedded Memories Show Growth
By Erach Desai
Analysis and trends
The challenge of micro-analyzing data that’s made available on a monthly basis is
that it is difficult to convert monthly data points into a trend. Of course, the beauty
of slicing the data on a monthly cycle is the potential to spot an emerging or evolving
trend. We attempt to overcome the imprecision of
monthly data points by looking at some rolling three- ...Continued on page 2
Is the Core Meltdown Just a False Alarm?
By Dave Bursky
behind the numbers
As time-to-market pressures continue to mount, the companies that are designing
complex application-specific integrated circuits (ASICs) are licensing more and more
intellectual property (IP). They hope to shorten their design cycles by using this IP,
which comprises embedded CPU cores, memory
blocks, MPEG encoders/decoders, USB interfaces, ...Continued on page 7
Synopsys Prepares for Future Growth in IP Segment
By Geoffrey James
IP Trends
When Synopsys began acquiring semiconductor intellectual-property (IP) firms
a few years ago, some industry pundits (including this writer) wondered whether
Synopsys CEO Aart de Geus knew what he was doing. Even though EDAC had
been tracking IP for years, many of us thought that
electronic design automation (EDA) was all about ...Continued on page 9
Design Interest to Peak in March, While Power
Ranges Rise
By John Blyler
Performance, power and area
This month, almost every new chip-design data metric was up—from total design
investigations to profiled power, clock speed, and die area (see Figure 1). These increases
were significantly large, exceeding the forecasts from last month. In order to better predict the
size of future changes, I’ve started tracking the moving
average of the total design profiles (see Figure 2).
...Continued on page 10

© 2007 Extension Media. All rights reserved.
Analysis and Trends
...Continued from page 1
month data. Design activity has nicely
bounced off some more-than-seasonally
weak levels last fall. Yet the year-over-year
trends are still negative (albeit less so).
The current issue of Chip Design Trends
reflects data that has been accumulated
through the month of January 2007. We’re
now tracking more than 41,000 unique
design investigations: system-on-a-chip
(SoC) design experiments, but not actual
design starts per se. We believe that the end
product of this rich and unique set of data is
a fairly accurate representation of how new,
complex, application-specific-integratedcircuit
(ASIC) design starts are trending.
In addition to tracking complexity across
a variety of metrics (as we have been
for the past three months), the current
issue of Chip Design Trends dives into
data for random-logic gate count and
embedded-memory megabits. Our goal
is to ascertain whether there’s a bigger
picture to be gleaned. In this issue, we also
have continued to drill down on the usage
of processor intellectual-property (IP)
central-processing-unit (CPU) cores.
First, let’s drill down into the overall and
geographic data. Figure 1 summarizes
the data and analysis for SoC designinvestigation
activity by geography. Recall
that we look at three-month rolling data
to arrive at some more tangible yearover-year
and sequential trends. The key
observations based on Figure 1 are:
• The rate of decline in total SoC
design investigations was the best
in five months. Nonetheless, design
investigations for the three months
ending in January 2007 declined
by 18% compared to a year ago. On
Three Months Ending Oct. ' 05 Jan. '06 Oct. '06 Jan. '07
N. America – Design Investigations 3,923 4,027 1,659 2,723
Year-over-year change -58% -32%
Sequential change +16% +3% -45% +64%
Europe – Design Investigations 1,472 968 920 671
Year-over-year change -38% -31%
Sequential change +82% -34% -23% -27%
Asia – Design Investigations 740 666 722 995
Year-over-year change -2% +49%
Sequential change -8% -10% -38% +38%
RoW – Design Investigations 166 86 180 326
Year-over-year change -45% +136%
Sequential change -27% -48% +109% +81%
Total – Design Investigations 6,301 5,747 3,481 4,715
Year-over-year change -45% -18%
Sequential change +20% -9% -36% +35%
Figure 1: The rate of year-over-year declines is moderating.
a sequential basis, however, SoC
design activity was up sharply by
35%. Keep in mind that this rise
was off of very weak levels for the
three months ending October 2006.
• Not surprisingly, trends in North
America continued to largely
mirror the overall trends, with the
actual percentage changes being
worse than the overall numbers.
Despite the nice sequential uptick,
we continue to be baffled by the
32% year-over-year decline.
• With the January 2007 data, Europe
and Asia went in different directions.
European design activity got worse
on both counts (sequential and year
over year), while Asia swung back
strongly on both counts.
• Design activity in the rest-of-world
(RoW) regions, as collected in our
data-set, continued to grow on a
gangbuster scale. However, the
rest-of-world regions were about
6% of overall design activity for
January 2007 compared to just
under 8% for December 2006.
• March 2007
Chip Design Trends

© 2007 Extension Media. All rights reserved.
Let’s score a point for the nice sequential
turnaround in the rolling three-month
data for January 2007. At the same time,
though, we must continue to mentally
note the year-over-year decline in overall
activity, which remains problematic to
explain away.
At first blush, it appears that the sharp
uptick in the under-50-mm2 die-size
range largely contributed to bringing the
average die size back toward 30 mm2.
Recall that we were optimistic last month
when there appeared to be a trend toward
slightly higher average die sizes.
Figure 2: Average die size is hovering around 35 mm2.
After we take our customary look at the
monthly cut of data by process technology
node, we will digress (pertinently) and
look at some die-size data by technology
node. For now, Figure 2 doesn’t provide
much weight in the case for more complex
designs.
In Figure 3, we capture the monthly trends
in SoC design experiments by process
technology node layered with the weighted
average of process node. After a solid four
consecutive months of lower average
process nodes (and headed toward 110
nm), the trend was derailed by the spike in
250-nm design activity. These intertwined
developments don’t augur well for a move
toward more complex design activity.
In recent months, we also have been
collecting die-size data on a per-processnode
basis. For this issue, we decided to
take a further look under the hood (so to
speak) to see if we could divine a deeper
understanding.
In Figure 4, we’ve juxtapositioned die-size
trends for 130 and 90 nm going back about
a year. For these sub-graphs, we computed
a “raw” average for die size. Although this
is still a weighted average, it isn’t as finely
calculated as the averages that we plot on
Figure 3: The average process node was derailed by a spike in 250-nm activity.
other graphs in our analysis. Curiously,
the moving average trend lines for both
process nodes seem to show similar
characteristics. (The 130-nm node does,
however, have a few more years of “learning
curve” built into it.) At these leading-edge
production nodes, it does seem that a
50 mm2 of die size is the manufacturing
“sweet spot.” Although the average die size
in Figure 2 may be drifting around 30
mm2, the leading-edge production nodes
are behaving as one would expect.
Figure 5 captures the frequency of design
investigations by the targeted number of
metal interconnect layers deployed for
leading-edge SoC designs. To look past
the gyrations in the weighted average,
we focus our attention on the six-month
trailing average. Consistent with the past
few months, we observe that we’re hovering
in the 6.3 to 6.4 layers-of-interconnect
range.
One interesting sub-plot is that the number
of 6LM design experiments bounced back
sequentially in January 2007. It exceeded
the number of 8LM designs.
Figure 6 graphs the average for the highest
targeted clock speed for each SoC design
experiment tracked by our data. The
average had rebounded nicely for two
consecutive months only to drop back to
about 200 MHz for January 2007. Despite
extending the trailing average from four
www.chipdesignmag.com/trends
March 2007 •

© 2007 Extension Media. All rights reserved.
to six months, the trend line still doesn’t
depict any specific pattern or anticipated
behavior.
Previously, we’ve observed that a trend
line of modestly higher clock speeds
would support a thesis of more complex
SoC designs—as long as the highest
clock speeds don’t spike up too much.
Unfortunately, neither the average nor
the moving average line up to provide any
credence to this thesis. One intriguing
development, however, is that the 100-
to-250-MHz clock-speed range narrowly
edged out the

© 2007 Extension Media. All rights reserved.
bits by month. Our key observations are
pretty much analogous to what we saw for
gate-count usage:
1. The under-1.0-Mbit category
is predominant by design
experiments.
2. The 1.0-to-2.5-Mbit and 2.5-to-
5.0-Mbit ranges have been picking
up steam in recent months.
Furthermore, the weighted-average trend
line for embedded-memory usage has
pretty much flatlined around 2.0 Mbits.
Again, one would think that rising
complexity would feature a slightly “up
and to the right” trend line. We shall
continue to monitor for any changes going
forward.
A Continuing Look at CPU
Semiconductor IP
Figure 10 captures the use of multiple
semiconductor-IP cores (non-memory)
on a monthly basis. Given macro trends
and intuitive logic, one would expect the
trend line for multiple semiconductor-IP
cores to be steadily increasing over time.
With a sharp rise in various multi-IP-core
instances, though, the weighted average
jumped sharply for January 2007. We
trust that this is a directional sign that is
sustained rather than some sort of “catch
up” in our monthly aggregated data set.
Figure 11 dives into a second layer of
detail: the use of unique CPU-core
instances on a monthly basis layered with
our weighted average trend line. In recent
months, the data continues to show a slow
but steady move toward one unique CPU
core instance per design. Yet the average
seems to be slowly nudging higher, which
is what we would like to see. The fact that
the average in recent months is still well
below year-ago levels remains somewhat
inexplicable at this juncture. (See Dave
Bursky's section for more details).
Figure 6: There is a lack of any trend-line in the highest clock speed.
Figure 7: Total I/O signals are settling around 300.
Figure 8: The average gate count is hovering between 2 and 3 million gates.
www.chipdesignmag.com/trends
March 2007 •

© 2007 Extension Media. All rights reserved.
Conclusion: Complexity Rising,
but Activity Moderating
Overall design activity for the month
of January 2007 continued to show
sequential improvement from the depths
that were reached in the fall of 2006. It
appears, however, that we had a surge in
activity at the 250-nm node. This surge
didn’t necessarily help our various metrics
of design complexity: die size, process
node, interconnect layers, highest clock
speed, and pin counts.
In this issue, we introduced graphs that
captured complexity based on gatecount
and embedded-memory usage. In
isolation, both metrics were somewhat
disappointing in that they depicted
relatively flattish behavior for the averages.
The one consolation factor, which adds
some credibility to the complexity
equation, was the apparent surge in nonmemory
semiconductor-IP instances.
Specifically, this surge was in unique
CPU-core instances.
In summary, the monthly data continues
to be engaging in that it is dynamic with
many moving parts. At the same time, it’s
hard to decipher meaningful trends from
monthly data points. Clearly, we don’t
have all of the answers or the relevant
explanations for the fluctuations in various
data points (and concomitant weighted
average trend lines).
Figure 9: Average embedded memory is currently in the 2.0-Mbit range.
Figure 10: Is there a spike or “catch up” in the usage of multiple cores?
Erach Desai, Chief Analyst, Chip Design
Trends
Figure 11: Is this the beginning of an uptrend in the number of CPU cores per design?
• March 2007
Chip Design Trends

© 2007 Extension Media. All rights reserved.
Behind the Numbers
...Continued from page 1
Ethernet ports, and more. Yet in the
consumer market in particular, products
tend to have short lives. As a result, designers
are looking for ways to extend the life of the
ASIC solutions that they’re crafting.
One approach that’s being adopted by many
companies is to embed programmable CPU
cores, which can be programmed to handle
specific tasks. In last month’s issue of Chip
Design Trends, Erach Dasai’s analysis
did note a decline in the use of embedded
processor cores. Yet that decline may be a
temporary market condition. It also could
be a conclusion based on an interpretation
of the data with which the semiconductor
intellectual-property vendors don’t agree. “It’s
very hard to really calculate the use of CPU
cores,” explains Richard Wawrzyniak, Senior
Analyst for ASICs at Semico Research
Corp., a market research company based
in Phoenix, Ariz. “There are many ways of
counting the cores and what, for example,
constitutes a CPU versus a dedicated
processor for audio or video.”
That view is echoed by Steve Liebson, the
Technology Evangelist at Tensilica Inc., a
provider of CPU-core IP in Santa Clara,
Calif. “Tensilica provides generic CPU cores
that the customer can configure as well as a
few application-optimized cores, which are
dedicated to audio and video processing, in
its recently released Diamond series. These
application-optimized cores are based
on the company’s Xtensa CPU core, but
include application-specific instructions to
handle specific audio or video operations.
The question is, do these cores get counted
as CPU cores or as function-specific blocks
of IP?” There is no absolute answer and
thus each analyst may interpret the data
differently.
Figure 1. ASIC designs are transitioning from the use of a single control processor (a la
the 1990s) to the use of distributed processing power in today’s complex SoC designs
(source: Tensilica Inc.).
The traditional view of the ASIC or systemon-a-chip
approach has changed over the last
decade, explains Steve Roddy, Tensilica’s Vice
President of Marketing. In 1997, the common
approach included a general control processor
and dedicated hardwired logic to perform
audio, video, and other support functions.
In 2007, however, the small features used
in today’s processes allow very area-efficient
and high-performance CPU cores to be used
to perform many tasks that were previously
done by hardwired logic (see Figure 1).
Each processing block can execute its own
firmware, thereby allowing designers to
change or enhance the functions in each block
independently just by changing the firmware.
This approach eliminates costly silicon respins
and can even allow field upgrades.
In another example of core counting,
ARM Ltd. of Cambridge, England offers
its AMR11MP core, explains Dave Steer,
Director of Segment Marketing. “This core
actually includes anywhere from one to four
CPUs, but is treated as a single block of IP.
But how does it get counted—as a single core
or as multiple cores? The debate will continue
for years as to how to count such blocks
of IP.” While also looking at parallel CPU
approaches, designers at ARC International
have developed single-instruction/multipledata
blocks of IP based on its ARC750
processor core. The company also offers
several application-optimized cores targeted
at media-processing and audio applications.
What ARM does see, though, is an increase in
the number of instances of its processor being
used on new ASIC designs. “The small size
and low power of the latest cores in the Cortex
family, for example, allow designers to use
multiple cores—each tackling an independent
task on the ASIC. By using programmable
cores, designers can also ‘future-proof ’ their
ASIC silicon since changes to the firmware
that executes on these deeply embedded
CPUs can be downloaded to upgrade the
functionality or fix a bug.”
ARM also has been enjoying an increase
in the number of new licensees—although
that rate of increase has slowed since the
company already has licenses with most
major companies, said Steer. The quarterby-quarter
results for the last three quarters
of 2006, for example, show increases in the
total number of licenses of 21, 14, and 15
for Q2, Q3, and Q4, respectively (see Figure
2). These licenses are split between new
licenses, derivative licenses, and upgrades
of existing licenses. ARM splits these
numbers even finer by looking at multi-use,
www.chipdesignmag.com/trends
March 2007 •

© 2007 Extension Media. All rights reserved.
Figure 2. The continuing growth in new-processor IP licenses
at ARM Ltd. shows a decrease in new licenses in the last
two quarters. But many customers are taking out additional
licenses for the company’s next-generation cores.
per-use, and term licenses (not shown).
According to Steer, about one-third are
new licensees. About one-quarter of all the
new licenses are from customers upgrading
their existing license arrangements to use
some of the new-generation cores to either
replace the older cores or to use them in
conjunction with the older cores.
Another IP provider experiencing an
increase in licenses, MIPS Technologies
Inc., has seen its licensing revenue increase
about 13% quarter over quarter with nine
new license agreements and seven new
customers. The company’s totals are now 117
licensed customers and almost 200 license
agreements. In its fiscal second quarter of
2007, the company recorded shipments of
89 million units—up 36% year over year—
with a total of 330 million units shipped in
the prior four quarters. It also is seeing strong
acceptance of the MIPS32 24K family cores,
which now have 33 licensees.
The use of multicore architectures also
has exploded in the entertainment market.
Each of the latest game consoles employs a
multicore solution. Microsoft’s Xbox360
and the Nintendo Wii both have processors
with multiple PowerPC cores, while the
Sony PS3 has a processor with up to nine
cores (a Power processor and
eight identical programmable
single-instruction/multipledata
processing engines).
Cell phones also are moving
to multiple-CPU-core
solutions. ARM already
estimates that on average,
there are about 1.5 ARM
processors in each cell phone.
As the phones include more
and more functionality,
they’ll have to include more
processors.
In such handheld
applications, power
consumption is a major concern. Chip power
is directly related to operating frequency. As
a result, the lower the frequency, the lower
the power consumption and thus the longer
the battery life. One approach to adding
more functionality leverages the fact that by
running a processor faster, it can do more. In
battery-powered systems, however, the result
is diminishing returns. The higher speed
translates into higher power consumption
and thus shorter battery life. The solution
comes from the old military tactic referred
to as “divide and conquer:” Use multiple
“slower” CPU cores to divide the compute
tasks into smaller blocks. Running the CPUs
slower reduces the power consumption. For
example, two cores running at 100 MHz
use less power than one core running at 200
MHz—even though more logic might be
needed to implement the multiple cores.
Software for all the embedded programmable
engines is another major concern, notes
Wawrzyniak. New software tools are
needed to allow programmers to rapidly
develop the programming for all of the onchip
processors. In addition to the tools,
such as compilers and debuggers, operating
systems must be designed to handle the high
levels of parallelism. ASIC design teams
are increasingly becoming dominated by
software engineers, observes Wawrzyniak.
Already, many companies report that more
than half of their development teams consist
of software engineers. These engineers
must develop the firmware and application
software needed to execute the intended
applications—everything from soft codecs for
audio to image processing and much more.
In addition to the CPU cores used in SoC
designs, there also is a growing market for
embeddable CPUs in field-programmablegate-array
(FPGA) fabrics. Although a
few FPGA vendors have integrated “hard”
CPU cores into the FPGA silicon, the most
popular approach is to use “soft” cores. These
register-transfer-level (RTL) descriptions
of the processor are integrated into the rest
of the logic and then synthesized with all
the other logic. The resulting configuration
can be downloaded into the FPGA
configuration memory as a bitstream.
FPGA vendors, such as Actel, Altera, and
Xilinx, have developed their own softprocessor
cores. They also have allowed
third-party CPU IP to be incorporated
into the logic configuration. The use of the
FPGA vendor’s home-grown soft cores is
hard to track, as there are no royalty fees
and customers typically don’t tell the world
what they’re doing inside the FPGAs. With
that said, however, Altera has gathered
some statistics. Many of its customers are
using more than one instance of its Nios II
family of embedded processor cores.
Is there a slowdown in the use of embedded
CPU cores? I don’t think so. Perhaps
there’s a small lull as companies transition
from generation to generation of the cores.
Overall, however, the momentum seems
to be sustained.
Dave Bursky is a Contributing Editor for Chip
Design and Chip Design Trends. Bursky also
is the Technical Editorial Manager at Maxim
Integrated Products Inc. in Sunnyvale, Calif.
• March 2007
Chip Design Trends

© 2007 Extension Media. All rights reserved.
IP Trends
...Continued from page 1
software and tools. IP was considered
just a way for design firms to generate
extra income. Although IP had value,
it wasn’t a technology that justified the
attention of a company that had mastered
EDA—the world’s most complex software
application.
Against expectations, though, IP has
turned out to be an important and growing
element of Synopsys’ business strategy.
According to the company’s annual report,
its IP business now accounts for $85
million of Synopsys’ $1.1 billion yearly
revenue. The company is heavily deployed
in interface and I/O IP—a segment that
continues to create new opportunity,
says Semico Analyst Rich Wawrzyniak.
“Evolving standards will continue to
raise the bar, creating opportunity for
companies deployed in this segment,” he
states. “Today’s computing environments
are all about communications and as long
as that remains true, we’re going to see
continuing activity in this area.”
Synopsys’ Group Director of IP and
Services Marketing, John Koeter, agrees.
“With wireless USB poised to take off
and new protocols like PCI Express Plus
and USB 3.0 around the corner, there’s
going to be increased demand for this
type of IP,” he says. Koeter notes that
Synopsys employs about 400 people in its
IP group—many of which are working on
new protocols. “This represents a major
R&D investment,” he emphasizes. “We’re
obviously serious.” The importance of IP
to Synopsys can also be gauged by the
company’s investment in testing, states
Navraj Nandra, Synopsys’ Director of
Marketing for Mixed Signal IP. “Interface
and I/O IP must undergo extensive
testing to make sure that it complies with
IP INTEREST MAP
Every month, we assess trends in the chip-design community based upon designer
usage of a leading IP portal. Data from the last three months illustrates that onchip
bus IP—the most important element of I/O and interface IP—remained
second only to the ever-popular digital-core and analog/mixed-signal IP segments.
With Synopsys moving heavily into mixed signal, the company will likely become
a player in two of the three most important IP segments.
standards, which is why we’ve now got
hardware testing labs dotted around the
U.S. and Canada,” he says.
Yet not everyone agrees that the interface
and I/O segment is that attractive. Former
Dataquest Analyst Gary Smith, who is
currently an independent consultant at
Gary Smith EDA, notes that as each
protocol comes out, there’s a limited
amount of time that Synopsys can charge
a premium for the related IP. “Synopsys
can offer it standalone as long as the
market will bear. But usually by nine
months, it has become a commodity. And
then they move it into their IP Library
offering, DesignWare,” he explains. For the
company, this is certainly not a disaster.
“These IP Libraries do make good money
and are a major competitive advantage for
Synopsys,” says Smith. But the tendency
to become commoditized makes this
type of IP less attractive than other, more
specialized segments like Digital Core. The
specialized segments command premium
royalties over a period of many years (see
the Sidebar: “IP Interest Map”).
Synopsys is already laying the groundwork
to get into more resilient segments of
the IP business, however. According to
Nandra, over a third of the company’s
IP engineers are working on numerous
mixed-signal projects. In addition, the
company is actively developing designs for
new memory formats like double-data-rate
DRAM (DDR2). While Synopsys has no
declared plans to enter other segments of
the IP business, such as Digital Core, the
company’s long experience in acquiring
technology firms leaves many options
open.
Geoffrey James, Contributing Editor, Chip
Design Trends
www.chipdesignmag.com/trends
March 2007 •

Performance, Power,
and Area
...Continued from page 1
© 2007 Extension Media. All rights reserved.
Moving averages are a statistical means to
track changes over a specified time period.
They allow one to spot trends by flattening
out large fluctuations. When used on a
monthly basis, these moving averages will
help to show whether the number of design
profiles is increasing or decreasing. Each
month’s numbers are added to the average
and the oldest numbers are dropped, which
causes the average to “move” over time. By
way of a technical analogy, moving averages
are similar to the lowpass filters used in
signal processing. They help to eliminate
the higher fluctuations.
Figure 1
No one method of forecasting is foolproof.
Yet the upward trend in the moving average
analysis in Figure 2—when combined with
the historical patterns in Figure 1—suggests
a continuing upward tendency for near-term
design-profile investigations. Historically,
our data suggests that design-investigation
activity peaks around the March timeframe.
Naturally, we’ll examine this trend more
closely in the coming months.
As mentioned earlier, all three key technical
parameters—power below 0.11 W, clock
speeds below 100 MHz, and die area smaller
than 50 mm squared—showed a significant
increase in interest. But one trend may be
deceiving: While designers performed more
tradeoffs at power levels at or below 0.11 W,
a significant number of designers used power
levels between 0.25 to 1 W (see Tables). In
fact, the power range from 0.25 to 1.0 W
saw a fourfold increase in interest—from
279 in December 2006 to 1155 in January
2007. This would suggest a rise in more
power-intensive applications in both mobile
and fixed devices. In future issues, this data
will be correlated to technology nodes and
other pertinent metrics.
Figure 2
When it’s added to our growing database
of historical trends, this month’s data
suggests that the months through March
2007 will be very significant for the chip
designers and managers who are exploring
new product designs. Significant trends
include a continuing interest in smaller
die sizes (less than 50 mm sq.), a leveling
off of clock speeds, and an unexpected
increase in total power investigations to
include the 0.25-to-1-W range.
John Blyler, Editorial Director
10 • March 2007 Chip Design Trends

© 2007 Extension Media. All rights reserved.
Jan 06 Feb 06 Mar 06 April 06 May 06 June 06 July 06 Aug 06 Sept 06 Oct 06 Nov 06 Dec 06 Jan 07
Total Design Profiles 1,248 1,254 1,927 1,162 1,574 1,901 2,113 1,496 951 1,571 812 1,439 2,658
Chip Power ≤ 0.11 W (Equivalent) 288 379 493 280 223 272 798 505 300 829 280 462 619
Avg CLK Speed ≤ 100 MHz (Equivalent)
689 767 1,011 739 755 1,232 1,382 911 743 1215 565 612 1,808
Die Area < 50 mm sq. (Equivalent) 974 1,108 1,598 890 839 1,431 1,668 1,194 771 1357 676 1,082 2,268
Percent change from previous month
Total Design Profiles -40% 0% 54% -40% 35% 21% 11% -29% -36% 65% -48% 77% 85%
Chip Power ≤ 0.11 W -6% 33% 42% -15% -20% 22% 193% -37% -41% 176% -66% 65% 34%
Avg CLK Speed ≤ 100 MHz -25% 11% 32% -27% 2% 63% 12% -34% -18% 64% -53% 8% 195%
Die Area ≤ 50 mm sq. -26% 15% 57% -16% -5% 71% 17% -28% -35% 76% -50% 60% 110%
By Total Chip Power
Designs Tracked by Power 749 761 1,277 1,156 1,574 1,901 2,112 1,496 950 1,570 812 1,439 2,657
≤ 0.11 W 173 230 327 279 223 272 798 505 300 829 280 462 619
0.25 W to 1.00 W 298 361 530 207 477 649 631 396 371 318 245 279 1,155
1.50 W to 4.00 W 181 103 227 466 308 639 478 406 218 304 276 428 679
5.00 W to 15.00 W 89 58 175 167 216 244 174 156 53 104 11 100 174
> 20.00 W 8 9 18 37 350 97 31 33 8 15 0 170 30
≤ 0.11 W (Equivalent to total) 288 379 493 280 223 272 798 505 300 829 280 462 619
Chip Design Trends
Data, Analysis, and Benchmarking on SOC Design
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