A Broadband High Efficiency Class-AB LDMOS ... - IEEE Xplore

A Broadband High Efficiency Class-AB LDMOS
Balanced Power Amplifier
L. Wu 1) , U. Basaran 1) , I. Dettmann 1) , M. Berroth 1)
T. Bitzer 2) , A. Pascht 2) ,
1) Institute of Electrical and Optical Communication Engineering, University of Stuttgart, Germany
Pfaffenwaldring 47, D-70550 Stuttgart, Germany
Tel: 49 711 685-7899 Fax: 49 711 6857900
Email: wu@int.uni-stuttgart.de Web: http://www.uni-stuttgart.de.int
2) Alcatel SEL AG, Holderaeckerstrasse 35, D-70499 Stuttgart, Germany
Abstract — In this paper, an LDMOS class-AB balanced
power amplifier with a 3-dB bandwidth of 800 MHz at a
center frequency of 2 GHz is presented. To the best of the
authors´ knowledge, this is the largest bandwidth reported
so far at these frequencies in an LDMOS technology. 50
Watt output power, high efficiency, high linearity and inputand
output-matching better than -10 dB have been achieved
over this large frequency band. An advanced stability
improvement is introduced in this paper.
I. INTRODUCTION
A broadband power amplifier is required for a multistandard
multi-frequency base-station transmitter. One of
the main concerns during the design of a broadband
power amplifier is the stability, since the transistors are
potentially unstable within a large bandwidth. This paper
gives an advanced method which improves and
guarantees the stability of a power amplifier, and
simultaneously reduces DC power consumption. Another
essential problem is the voltage standing-wave ratio
(VSWR) at the power amplifier output due to the power
match instead of a conjugate match. The balanced
structure is therefore used to significantly reduce the
input and output VSWR, so that the power amplifier can
easily be cascaded with its driver or the other
components in the transmitter. LDMOS power amplifiers
are widely used in modern wireless communication
systems due to their better intermodulation distortion
(IMD) performance compared to competing technologies
[1] and relatively low cost. In this paper, we present a
balanced class-AB LDMOS power amplifier. Using
broadband matching networks, this power amplifier has a
3-dB bandwidth of 800 MHz with the center frequency
of 2 GHz, therefore, excellent performance both in
UMTS (2110-2170 MHz) and in GSM1800 (1805-1880
MHz) frequency bands have been shown by the
measurement.
In Section II, methods to realize the broadband
matching networks are shown. Section III introduces
concisely the balanced amplifier. In Section IV we
propose a straightforward method to improve the stability
of a power amplifier. The experimental results and
conclusions follow in Sections V and VI.
Fig. 1. Broadband matching with multisection transformer.
(a) input matching (b) output matching
II. BROADBAND MATCHING
To obtain the maximum output power, the reference
impedance (normally 50 Ohm) must be transformed to
the optimum input and output impedance Z in_opt and
Z out_opt of the transistor through the matching networks. It
is in principle required that the bandwidth of an amplifier
should not be degraded by the impedance transformation.
However, it is very difficult to fulfill this task in reality.
As a power device, an LDMOS transistor has a large
breakdown voltage due to the additional drift region at its
drain. But this additional drift region involves a larger
drain-source capacitance, which causes an optimum
output impedance of the device well below 50 Ohm. In
this work, the Motorola LDMOS transistor
MRF21030SR3 has been used. Z in_opt and Z out_opt of this
device are 14.6 - j9.4 Ohm and 3.4 - j0.37 Ohm at 2.14
GHz, respectively. To obtain a broad-band matching,
multisection transformers are designed using the Smith
chart as shown in Fig. 1. Since the optimum output
impedance is approximately a real value, two-section
quarter-wave transformer can be almost directly used.
The optimum input impedance is a complex value,
therefore, the 50 Ohm load can be firstly transformed to a
real impedance of 24 Ohm, then be further transformed
to the 14.6 - j9.4 Ohm with an appropriate length of the
transmission line. The conception of both transformations
is retaining a lower quality factor Q, which implies a
broader bandwidth for a given resonance frequency.

Z in_opt
V d
Z out_opt
R
RF-in
input
matching
network
Quadrature
hybrid coupler
V g
A
V d
Output
matching
network
Quadrature
hybrid coupler
50
(a)
R
(b)
50
input
matching
network
Z in_opt
B
Z out_opt
Output
matching
network
RF-out
R
R
V g
(c)
(d)
Fig. 2. Balanced power amplifier
Fig. 3. Four types of resistive loading.
III. BALANCED POWER AMPLIFIER
Balanced amplifiers, whose configuration is shown in
Fig. 2, are attractive due to very low VSWR and
excellent cascade-ability. Two identical amplifiers A and
B are connected in parallel through two quadrature
hybrid couplers, which operate as a power divider at the
input and a power combiner at the output, respectively.
Quadrature hybrid couplers are 3-dB directional couplers
with a 90° phase difference in the outputs of the through
and coupled arms. Therefore, at the input of the balanced
amplifier, the two reflected signals from the two
individual amplifiers compensate each other since they
are 180° out of phase, so that the balanced amplifier has
ideally a VSWR of 1 at its input. The same are the two
reflected signals at the output. Therefore, VSWR of a
balanced amplifier depends on the coupler, not on each
individual amplifier. The forward transmitted signals of
the two individual amplifiers are again in phase at the
output, due to the same length of their routes. The S-
parameters of a balanced amplifier can be given as
follows [2]
S11 0.
5 S11A
S11B
(1)
S21 0.
5
S21A
S21B
(2)
S12 0.
5
S12
A
S12B
(3)
S22 0.
5
S22
A
S22B
. (4)
It can be seen that the magnitude of S 11 and S 22 should be
zero, if the two individual amplifiers are absolutely
identical. Excellent stability can therefore be expected
because of the perfect feature of VSWR. In case of entire
identity of two individual amplifiers, the gain of a
balanced power amplifier remains the same as that of a
single amplifier, according to (2). Though the gain of a
balanced power amplifier will not be doubled in spite of
the usage of two devices, the maximum accomplishable
output power of a balanced power amplifier is twice that
of a single amplifier, which is naturally very desired for a
power amplifier design. However, except lots of
advantages, double cost of a balanced power amplifier
due to the usage of two devices is not negligible.
Fig. 4. Stable range (grey range) in Smith charts. (a) without
shunt resistor. (b) with shunt resistor.
V d
Z out_opt
R
Output
matching
network
Fig. 5. Advanced method for stability improvement.
IV. STABILITY IMPROVEMENT
50
Although a balanced amplifier shows an outstanding
stability due to its perfect VSWR, each individual
amplifier of it must also be designed to be stable in its
operating region. Simulations show that MRF21030SR3
is only conditionally stable over a large bandwidth. To
improve the stability, four choices of resistive loading to
the transistor are given in [3]. They are series or shunt
resistor connected at the input or the output of the

transistor as shown in Fig. 3. Resistive loading at the
input is usually not used since it produces a significant
deterioration in the noise performance of the amplifier. A
series resistor at the output is also not so popular since it
can reduce the gain of the amplifier dramatically.
Therefore, suitable shunt resistors R are selected and
separately connected to the drain of each transistor. The
stable ranges in Smith charts simulated at 1.85 GHz
become thereby much larger as illustrated in Fig. 4.
However, the shunt resistors consume large DC power
reducing the power added efficiency (PAE) dramatically.
On the other hand, to ensure the good RF performance of
the power amplifier, resistors of surface mount device
(SMD) should be used, which have only very small
dimensions. However, such devices can be easily
destroyed by a large current resulting in the instability of
the power amplifier again. A new configuration for the
stability improvement is introduced in our work by
adding a series capacitor C to each shunt resistor as
shown in Fig 5. This capacitor prevents a DC current
flowing through the shunt resistor, reduces the total DC
power consumption and protects the resistor R against a
large current. Fig. 6 depicts the simulated current flowing
through each shunt resistor R with or without C, when
the output power is 40 dBm. We remark that the DC part
of the current in (a), which has a magnitude of about 0.52
A, is deleted with the aid of C. Hence, a DC current of
about 1.04 A can be saved for the balanced amplifier.
The series capacitance C must be sufficiently large, in
order to avoid an impedance transformation from the
resistance R selected by stability improvement.
Therefore, the improvement of the stability obtained by
the shunt resistor remains.
current on R, mA
800
700
600
500
400
V. EXPERIMENT
A power amplifier has been fabricated using the
Motorola LDMOS transistor MRF21030SR3 as shown in
Fig. 7. The bias voltages are V g = 3.8 V and V d = 26 V. It
has been fabricated on a 0.81 mm-thick RO4003
substrate, which has a relative permittivity of 3.38 and a
conductor thickness of 35 µm. Wilkinson couplers have
been used as power divider and combiner. Because a
Wilkinson divider has two in phase output signals, it is
necessary to shift the phase of the signal before the upper
amplifier and the phase of the signal after the lower
amplifier by 90° using quarter-wave transmission-lines.
Fig. 7. Photograph of the fabricated balanced power
amplifier.
S-parameter, dB
/4-T. L.
20
10
0
-10
-20
S21
-30
S11
S22
-40
1.5 1.7 1.9 2.1 2.3 2.5 2.7
freqency, GHz
/4-T. L.
300
0 200 400 600
800
time, ps
(a)
Fig. 8. Measured magnitudes of the S-parameters.
200
current on R, mA
100
0
-100
-200
0 200 400 600
800
time, ps
(b)
Fig. 6. Simulated current flowing through the shunt resistor R
in the time domain. (a) without C; (b) with C
P out, dBm & PAE, %
P in, dBm
P out at 2.14 GHz
P out at 1.85 GHz
PAE at 2.14 GHz
PAE at 1.85 GHz
gain at 2.14 GHz
gain at 1.85 GHz
Fig. 9. Measured output power, PAE and power gain.
power gain, dB

accomplishes 50 W (47 dBm) at both frequencies. The
1-dB compression points are located at 46 dBm. A PAE
of 35.5% has been achieved at 1.85 GHz for the
maximum output power. At 2.14 GHz, the PAE is as high
as 42.5% for the maximum output power. Even with the
consideration of 6 dB back off from the 1-dB
compression point, a PAE of 20% is obtained at this
frequency. Due to the limited output power of the two
signal generators, the third order intermodulation
distortion versus the output power has been measured
only up to P out = 40 dBm (but just 6 dB back off point in
UMTS band) as shown in Fig. 10. IMD3 better than -
42.5 dBc at 1.85 GHz and than -39 dBc at 2.14 GHz have
been obtained when the output power is lower than 40
dBm.
Fig. 10. Measured third order intermodulation distortion
versus output power.
The 180° out of phase of the two reflected signals at the
input and the output of the balanced amplifier is realized.
The in phase signals at the output of the balanced
amplifier, which are forward transmitted from the two
individual amplifiers can also be obtained in this manner.
Measured S-parameters are shown in Fig. 8. A linear
gain of about 12 dB has been obtained. This power
amplifier has a 3-dB bandwidth of 800 MHz with the
center frequency of 2 GHz, so that it can be adopted
simultaneously both in UMTS and in GSM1800 system.
Magnitudes of S 11 and S 22 of this power amplifier are in
the frequency range of interest between -10 dB and
-30dB. Fig. 9 presents the input-referred output power
P out , PAE and the power gain measured at 1.85 GHz and
2.14 GHz, separately. The maximum output power
VI. CONCLUSION
A 50 W balanced power amplifier using LDMOS
transistors has been developed. Broad bandwidth, high
efficiency, good linearity and low VSWR prove this
design concept to be a good candidate for multi-standard
multi-frequency base-station transmitters.
REFERENCES
[1] S. R. Novis and L. Pelletier, ‘IMD parameters describe
LDMOS device performance’, Microw. RF, vol. 37, pp.
69-74, July 1998.
[2] Guillermo Gonzalez, Microwave transistor amplifiers,
Second edition, pp. 330, Prentice Hall Inc., New Jersey,
1997.
[3] Guillermo Gonzalez, Microwave transistor amplifiers,
Second edition, pp. 225–228, Prentice Hall Inc., New
Jersey, 1997.