Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

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Specification Index 1.01 Project No. RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 6 Development Production S. Schreiber 2007-08-24 Furthermore, one or more slave devices are connected to the I 2 C-bus, where each slave device must have a unique I 2 C-address. An I 2 C bus can be free and there are start conditions, repeated start conditions, stop conditions, and bit transfers on an I 2 C-bus (Figure 2). Both SCL and SDA are high while the I 2 C bus is free; all of the SCL and SDA outputs are high. (All open-drain outputs on a line form a wired-AND.) The start condition S is a falling edge of the SDA line, when the SCL line is (still) high. The SCL line is pulled to low subsequently. A start condition S is generated only by a master. The SCL line is low before a bit transfer (subsequent to a start condition or a bit transfer). The transmitting device pulls the SDA line low or releases it to high according to the desired data bit first. At next the master generates a rising edge on the SCL line and a falling edge on SCL subsequently. (When SCL is high between the rising and falling edge, SDA must not change its state, because it would generate a start condition or a stop condition.) The SCL line is low again after transmitting the bit. The SCL line is always driven by the master, but the SDA line is driven by the transmitting device (either the master or the slave which was addressed before by the master). A slave can slow down the transfer by pulling the SCL line to low after the falling edge (clock stretching). The master has to realize that the slave pulls the SCL line to low. Since the SCL outputs of the master and the slave form a wired-AND, the SCL line will be low until both the master and the slave are able to continue. The SCL line is low before a stop condition P (subsequent to a bit transfer). The SDA line is pulled to low if it was not low before. The SCL line is released to high. A rising edge is generated on the SDA line subsequently; and the I 2 C-bus is free. A stop condition P is generated only by a master. A master also can generate a repeated start condition Sr that starts a new transfer after the bus has been acquired. The SDA line is released to high if it was not high before. The SCL line is released to high. A falling edge is generated on the SDA line subsequently. A stop condition P and a start condtion S, which are generated by a master, can be replaced by a repeated start condition Sr. A master uses a repeated start condition Sr in order to start a new transfer, but prevents another master device from acquiring the I 2 C bus. SDA SCL free bus start condition S data bit bit transfer Figure 2 I 2 C-bus lines and common conditions data bit bit transfer another bit transfers another bit transfers stop condition P repeated start condition Sr free bus another bit transfers 7007
Specification Index 1.01 Project No. RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 7 Development Production S. Schreiber 2007-08-24 Addressing a Slave and Performing Data Transfer Each slave, which is connected to the I 2 C-bus, must have a unique I 2 C-address. An I 2 C-address can be either 7 bits wide (legacy 7-bit addressing) or 10 bits wide. Slave devices with 7-bit addressing and 10-bit addressing can be mixed on an I 2 C-bus, because 10-bit addressing is upwards-compatible. 7-bit addressing If a master wants to transfer any data to (write) or from (read) a slave which has a 7-bit address, the master generates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 3). At next the master transmits one (address-) byte (8 bits with bit transfers). These 8 bits are the 7-bit address (most significant bit at first), followed by one bit R/W, which specifies the desired direction of the transfer. If the R/W-bit is 0, it is a write transfer (the master transmits data bits; the slave receives them). If the R/W-bit is 1, it is a read transfer (the master receives data bits; the slave transmits them). Each slave has to recognize the start condition S and has to receive the subsequent address-byte. A slave will compare the received 7-bit address with its own unique address. If the address matches, a slave is addressed by the master. Other slaves, which are not addressed, will continue waiting for another start condition S (or a repeated start condition Sr). With the nineth bit transfer an acknowledge bit A is transferred from the slave to the master (in the opposite direction to the transfer of the preceding address-byte). The addressed slave has to transfer a low acknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I 2 C-bus enters its free state. addressing a slave write transfer 7-bit 0 0 8-bit 0 8-bit 0/1 free S address RW A+ data byte A+ data byte A P free from master to slave from slave to master Figure 3 Write transfer using a 7-bit address S start condition RW R/W direction bit A+ acknowledge-bit (SDA line is low) A acknowledge-bit (SDA line is low or high) P stop condition 7007
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Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

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