Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

Specification 

Index 1.01 

Project No. 

RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 1 

Development 

Production S. Schreiber 2007-08-24 


of 

RTRM08 

Transceiver Module 

Easywave I 2 C 

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Index 1.01 

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Revision History 

Index Releases 

0.90 Initial Release. 

1.00 Section 1 and section 2.1: 

Options for the antenna are mentioned now. 

Section 2.3: 

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Some figures have been corrected. The acknowledge bit A- after the final data byte of 

a read transfer is labeled with “1“ now (Figure 4, Figure 5, Figure 7, Figure 8). 

It is stated now that the current implementation interrupts any receive attempt of 

Easywave telegrams while the persistent storage is written (RX_USERDATA0 and 

RX_USERDATA1 registers). 

It is stated that any bit is cleared in the RX_LN_CHXXX registers when ELDAT ships the 

transceiver module RTRM08. 

1.01 Section 1, section 2.1, and section 3.2: 

The upper limit of the power supply's operational range of 5.5 V has been decreased to 

5.25 V.


Index 1.01 

Project No. 


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Table of Contents 

1 General Description...........................................................................................................................4 

2 Functional Description...................................................................................................................... 4 

2.1 Pin Definition.............................................................................................................................4 

2.2 Power up and Reset....................................................................................................................5 

2.3 I2C-bus.......................................................................................................................................5 

Signal Lines of the I2C-bus........................................................................................................5 

Addressing a Slave and Performing Data Transfer....................................................................6 

Accessing the Transceiver Module.......................................................................................... 12 

Initialization on Reset.............................................................................................................. 19 

Receiving of Easywave Telegrams.......................................................................................... 19 

Learning of Easywave Telegrams............................................................................................ 21 

Delete Learned Easywave Telegrams.......................................................................................21 

Transmitting of Easywave Telegrams......................................................................................22 

3 Electrical Characteristics................................................................................................................. 23 

3.1 Absolute Maximum Ratings.................................................................................................... 23 

3.2 Operating Conditions...............................................................................................................23 

3.3 Characteristics..........................................................................................................................24 

4 Mechanical Specification................................................................................................................ 24 

Figures 

Figure 1 Component side view of the transceiver module................................................................... 4 

Figure 2 I2C-bus lines and common conditions...................................................................................6 

Figure 3 Write transfer using a 7-bit address........................................................................................7 

Figure 4 Read transfer using a 7-bit address.........................................................................................7 

Figure 5 Combined write and read transfer using a 7-bit address........................................................ 8 

Figure 6 Write transfer using a 10-bit address....................................................................................10 

Figure 7 Read transfer using a 10-bit address.....................................................................................11 

Figure 8 Combined write and read transfer using a 10-bit address.................................................... 12 

Figure 9 Writing into registers of the transceiver module..................................................................13 

Figure 10 Reading out registers of the transceiver module................................................................ 13 

Figure 11 Sequence when receiving Easywave telegrams..................................................................20 

Figure 12 Sequence when transmitting Easywave telegrams............................................................. 23 

Figure 13 Drawing of the transceiver module.................................................................................... 26 

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1 General Description 

Features of the RTRM08 transceiver module: 

– Sends and receives Easywave at 868.3 MHz, FSK modulation. 

– Whip antenna. Other options are available on request: coaxial connectors or an antenna via the module's 

connector. 

– High output power of +9 dBm (at 5 V power supply) . 

– Each module can transmit 32 different Easywave telegrams which have unique serial numbers. 

– Up to 32 Easywave transmitters can be taught in the RTRM08 Easywave module. The RTRM08 stores 

16-bit user data associated with each Easywave transmitter. Persistent storage (EEPROM). 

– I 2 C-bus, 100 kHz clock rate (Standard Mode), slave only. 

– Fixed I 2 C address, which is 1100010 (7-bit, excluding the R/W-bit). 

– A separate request output allows to work without any polling. 

– Operational range of power supply: 2.1 V to 5.25 V. 

– Power down state with low current consumption when being inactive. 

– LEDs indicate transmit and receive operation (optional). 

– Approval standards EN 300 220-1 V1.3.1 (2000-09) and EN 300 220-3 V1.1.1 (2000-09). 

2 Functional Description 

2.1 Pin Definition 

Pins are numbered as shown in Figure 1. 

LED (receive, green) 

LED (transmit, yellow) 

1 2 3 4 5 6 7 8 9 10 11 12 

whip antenna 

Figure 1 Component side view of the transceiver module 

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Pin number Signal name Signal direction Description 

1 VCC - Power supply (2.1 V ...5.25 V). 

2 GND - Ground. 

3 / RESET in Reset. Active low. 

4 SDA bidirectional (open-drain) I 2 C serial data I/O. 

5 SCL bidirectional (open-drain) I 2 C synchronous serial clock I/O. 

6 / REQ out (open-drain) Request output. It indicates whether an 

Easywave telegram could be received and 

whether a received Easywave telegram is 

over. Active low. 

7 - 12 (NC) - Pins are not allowed to connect to any circuit. 

There are options for the antenna available, for example, coaxial connectors or an antenna via the module's 

connector. Please contact ELDAT. 

2.2 Power up and Reset 

The module's / RESET signal is not allowed to be high until the power supply is in the operational range. The 

module is in inactive state subsequently; it can be controlled via the I 2 C-bus. 

The / REQ output of the module goes to (active) low until the module's rx mode is altered. 

The module also can be reset at any time independent from its former state by asserting the / RESET signal. 

2.3 I 2 C-bus 

The SCL and the SDA pin are the I 2 C-bus as defined in the “THE I 2 C-BUS SPECIFICATION VERSION 2.1“ 

(January 2000), document order number 9398 393 40011 by Philips. 

A short discussion of the I 2 C-bus follows in this section. If both this specification of the RTRM08 transceiver 

module and the referred “THE I 2 C-BUS SPECIFICATION VERSION 2.1“ document define a specific detail, 

the specification of the RTRM08 transceiver module has informational characteristics only. 

The I 2 C clock rate of the transceiver module can be up to 100 kHz (Standard Mode). 

Signal Lines of the I 2 C-bus 

The I 2 C-bus is a 2-wire bus; it has a bidirectional serial clock line SCL and a bidirectional serial data line SDA. 

Both SCL and SDA are combined inputs and open-drain outputs. There must be one pullup-resistor on each 

of the SCL and the SDA line. The RTRM08 transceiver module I 2 C PHY does not include these pullupresistors. 

A device connected to a bus can be either a master or a slave. A master device is able to acquire the I 2 C-bus 

and initiate a transfer from (read) or to (write) a specified slave. The master generates the clock on the SCL 

line in order to transfer the serial data bits. The slave can slow down the transfer if it can't transmit or receive 

data bytes fast enough (clock stretching, see below). The master has to terminate the transfer and release 

the I 2 C-bus either successfully or due to a fail. 

The SDA line is driven by the device which transmits data bits: it is either a master or a slave. 

One or more master devices can be connected to the I 2 C-bus. This specification covers examples with one 

master only, but the transceiver module also works on I 2 C-busses with more than one master (multi-master). 

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Furthermore, one or more slave devices are connected to the I 2 C-bus, where each slave device must have a 

unique I 2 C-address. 

An I 2 C bus can be free and there are start conditions, repeated start conditions, stop conditions, and bit 

transfers on an I 2 C-bus (Figure 2). 

Both SCL and SDA are high while the I 2 C bus is free; all of the SCL and SDA outputs are high. (All open-drain 

outputs on a line form a wired-AND.) 

The start condition S is a falling edge of the SDA line, when the SCL line is (still) high. The SCL line is pulled to 

low subsequently. A start condition S is generated only by a master. 

The SCL line is low before a bit transfer (subsequent to a start condition or a bit transfer). The transmitting 

device pulls the SDA line low or releases it to high according to the desired data bit first. At next the master 

generates a rising edge on the SCL line and a falling edge on SCL subsequently. (When SCL is high between 

the rising and falling edge, SDA must not change its state, because it would generate a start condition or a 

stop condition.) The SCL line is low again after transmitting the bit. The SCL line is always driven by the 

master, but the SDA line is driven by the transmitting device (either the master or the slave which was 

addressed before by the master). 

A slave can slow down the transfer by pulling the SCL line to low after the falling edge (clock stretching). The 

master has to realize that the slave pulls the SCL line to low. Since the SCL outputs of the master and the 

slave form a wired-AND, the SCL line will be low until both the master and the slave are able to continue. 

The SCL line is low before a stop condition P (subsequent to a bit transfer). The SDA line is pulled to low if it 

was not low before. The SCL line is released to high. A rising edge is generated on the SDA line 

subsequently; and the I 2 C-bus is free. A stop condition P is generated only by a master. 

A master also can generate a repeated start condition Sr that starts a new transfer after the bus has been 

acquired. The SDA line is released to high if it was not high before. The SCL line is released to high. A falling 

edge is generated on the SDA line subsequently. A stop condition P and a start condtion S, which are 

generated by a master, can be replaced by a repeated start condition Sr. A master uses a repeated start 

condition Sr in order to start a new transfer, but prevents another master device from acquiring the I 2 C bus. 

SDA 

SCL 

free 

bus 

start 

condition 

S 

data bit 

bit 

transfer 

Figure 2 I 2 C-bus lines and common conditions 

data bit 

bit 

transfer 

another bit 

transfers 

another bit 

transfers 

stop 

condition 

P 

repeated start 

condition 

Sr 

free 

bus 

another bit 

transfers 

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Addressing a Slave and Performing Data Transfer 

Each slave, which is connected to the I 2 C-bus, must have a unique I 2 C-address. An I 2 C-address can be either 

7 bits wide (legacy 7-bit addressing) or 10 bits wide. Slave devices with 7-bit addressing and 10-bit 

addressing can be mixed on an I 2 C-bus, because 10-bit addressing is upwards-compatible. 

7-bit addressing 

If a master wants to transfer any data to (write) or from (read) a slave which has a 7-bit address, the master 

generates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 3). At next 

the master transmits one (address-) byte (8 bits with bit transfers). These 8 bits are the 7-bit address (most 

significant bit at first), followed by one bit R/W, which specifies the desired direction of the transfer. If the 

R/W-bit is 0, it is a write transfer (the master transmits data bits; the slave receives them). If the R/W-bit is 1, 

it is a read transfer (the master receives data bits; the slave transmits them). 

Each slave has to recognize the start condition S and has to receive the subsequent address-byte. A slave 

will compare the received 7-bit address with its own unique address. If the address matches, a slave is 

addressed by the master. Other slaves, which are not addressed, will continue waiting for another start 

condition S (or a repeated start condition Sr). 

With the nineth bit transfer an acknowledge bit A is transferred from the slave to the master (in the opposite 

direction to the transfer of the preceding address-byte). The addressed slave has to transfer a low 

acknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communication 

will proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the 

I 2 C-bus enters its free state. 

addressing a slave write transfer 

7-bit 0 0 8-bit 0 8-bit 0/1 

free S address RW A+ data byte A+ data byte A P free 

from master to slave 

from slave to master 

Figure 3 Write transfer using a 7-bit address 

S start condition 

RW R/W direction bit 

A+ acknowledge-bit (SDA line is low) 

A acknowledge-bit (SDA line is low or high) 

P stop condition 

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addressing a slave read transfer 

7-bit 1 0 8-bit 0 8-bit 1 

free S address RW A+ data byte A+ data byte A- P free 



Figure 4 Read transfer using a 7-bit address 




A- acknowledge-bit (SDA line is high) 


If it is a write transfer, the master continues transmitting the data bytes which the master wants to write into 

the addressed slave (Figure 3). If it is a read transfer, the addressed slave will transmit the data bytes 

synchronous to the master according to the serial clock which the master generates (Figure 4). If addressing 

of a slave went successfully, at least one data byte has to be transferred. The master isn't allowed to 

generate a stop condition immediately after transferring the desired slave address. 

Data bytes (8 bits) are transferred with their most significant bit at first. After each data byte an acknowledgebit 

A is transferred from that device, which received the preceding data byte to the device, which transmitted 

the data byte before: the acknowledge-bit is transferred in the opposite direction to the preceding transfer of 

the data byte. 

If the master receives a low acknowledge-bit A+ (means acknowledge) while a write transfer, the master can 

continue writing into the slave. If the master receives a high acknowledge-bit A- while a write transfer, it will 

terminate the transfer with a stop condition P. 

If the master transmits a low acknowledge-bit A+ to the slave (means acknowledge) while a read transfer, the 

master has to continue reading the slave's data. If the master transmits a high acknowledge-bit A- to the 

slave due to any reason while a read transfer, the master has to terminate the transfer with a stop condition P 

subsequently. 

Each transfer is terminated by the master, which generates a stop condition P. The master also can 

terminate a transfer with a repeated start condition Sr which addresses a slave again and initiates a new 

transfer. Subsequent to a repeated start condition Sr the sequence is just as after a start condition S. 

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addressing a slave write transfer 

7-bit 0 0 8-bit 0 8-bit 0/1 

free S address RW A+ data byte A+ data byte A 

addressing a slave read transfer 

7-bit 1 0 8-bit 0 8-bit 1 

Sr address RW A+ data byte A+ data byte A- P free 



Figure 5 Combined write and read transfer using a 7-bit address 


Sr repeated start condition 






Often a master wants to perform a read transfer immediately after a write transfer (Figure 5). The master can 

use a repeated start condition Sr in place of a separated stop condition P and a start condition S after the 

write transfer and before the read transfer. 

Some 7-bit addresses are reserved and are not allowed to be used as slave-address. The 7-bit addresses 

11110xx (binary) are not allowed to be used as 7-bit slave address, because they initiate 10-bit addressing, 

see below. (Please refer to Philips' I 2 C specification for further information about reserved addresses.) 

10-bit addressing 

If a master wants to transfer any data to (write) or from (read) a slave that has a 10-bit address, the master 

generates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 6). At next 

the master transmits the bit pattern 11110 and the two most significant bits of the 10-bit address (most 

significant bit at first), which are followed by one R/W-bit. The R/W-bit must be always 0 (means write 

transfer) for compatibility with 7-bit addressing, even though there is a read transfer desired. The mentioned 

bit pattern, 2 bits of the address, and the R/W-bit are 8 data bits (one byte), which the master transmits. 

Each slave has to recognize the start condition S and has to receive the subsequent byte. A slave will check 

the bit pattern 11110, compare the received 2-bit part of the address with its own unique address, and check 

the R/W-bit. If the two address bits match and R/W is 0, a slave continues receiving the addressing of the 

master. Other slaves, which are not addressed, will continue waiting for another start condition S (or a 

repeated start condition Sr) including all slaves which have a 7-bit address. Since the 7-bit address 11110xx 

is reserved, not any 7-bit slave has a matching address. 

With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master (in the opposite 

direction to the transfer of the preceding byte). Any addressed slave has to transfer a low acknowledge-bit A+ 

(means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; when 

the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I 2 C-bus enters its 

free state. 

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At next the master generates a repeated start condition Sr and transmits the eight remaining least significant 

bits of the 10-bit address (most significant bit at first). 

Any slave which was addressed by the two most significant address bits will compare the received eight least 

significant address bits with its own unique address. If the address bits match, a slave is addressed by the 

master. Other slaves, which are not addressed, will continue waiting for another start condition S (or a 

repeated start condition Sr). 

With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master again (in the 

opposite direction to the transfer of the preceding byte). The addressed slave has to transfer a low 




If a write transfer is desired, the master continues transmitting the data bytes and will terminate the transfer 

exactly as it is described on 7-bit addressing (Figure 6). 

addressing a slave 

(high part of address) 

2-bit 0 0 8-bit 0 

free S 11110 address RW A+ Sr address A+ 

write transfer 

8-bit 0 8-bit 0/1 

data byte A+ data byte A 



Figure 6 Write transfer using a 10-bit address 


(low part of address) 

P free 







If a read transfer is desired, the master generates a repeated start condition Sr after it has addressed a slave 

(10-bit address) successfully (Figure 7). At next the master transmits the bit pattern 11110, the two most 

significant bits of the 10-bit address (most significant bit at first), which are followed by one R/W-bit again. 

The R/W-bit must be 1 now (means read transfer). 

The slave which was addressed before the repeated start condition Sr (but not any other slave) will check the 

bit pattern 11110, compare the received 2-bit part of the address with its own unique address, and check the 

R/W-bit (must be 1) again. If each bit matches, the considered slave is addressed by the master for a read 

transfer. Other slaves, which are not addressed, will continue waiting for another start condition S (or a 

repeated start condition Sr). 

With the nineth bit transfer an acknowledge bit A is transferred again from a slave to the master (in the 

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opposite direction to the transfer of the preceding byte). The addressed slave has to transfer a low 




The master receives the data bytes from the slave at next and will terminate the transfer exactly as it is 

described on 7-bit addressing. 





2-bit 0 0 8-bit 0 


addressing the slave for read 

transfer (high part of address) 

2-bit 1 0 8-bit 0 8-bit 1 

Sr 11110 address RW A+ data byte A+ data byte A- P free 



Figure 7 Read transfer using a 10-bit address 

read transfer 







Often a master wants to perform a read transfer immediately after a write transfer (Figure 8). The master can 

also address a slave (10-bit addressing) for a read transfer immediately after a write transfer was performed. 

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2-bit 0 0 8-bit 0 


write transfer 

8-bit 0 8-bit 0/1 

data byte A+ data byte A 

addressing the slave for read 

transfer (high part of address) 

2-bit 1 0 8-bit 0 8-bit 1 

Sr 11110 address RW A+ data byte A+ data byte A- P free 



read transfer 

Figure 8 Combined write and read transfer using a 10-bit address 

Accessing the Transceiver Module 








The transceiver module is a slave and has a fixed I 2 C address (7-bit), which is 1100010 (binary, excluding 

the R/W-bit). Other fixed I 2 C addresses (7-bit or 10-bit) are available on request. 

The module holds all information in registers which can be written or read via the I 2 C-interface. Each register 

is 8 bits wide (one byte) and has a specific register address. The register address also is 8 bits wide. 

The module maintains a register address pointer, which contains the register address of the register that is 

written or read at next. 

When a master does a write transfer to the transceiver module, the module takes the first data byte of the 

transfer as desired register address: it initializes its register address pointer with the transferred data byte 

(Figure 9). Each subsequently transferred data byte is written into the register which the current register 

address pointer specifies. The register address pointer is incremented by one after each write, so the next 

transferred data byte is written into the next register. 

When a master does a read transfer from the transceiver module, each data byte is read out of the register 

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which the current register address pointer specifies (Figure 10). The register address pointer is incremented 

by one after each read, so the next transferred data byte is read out of the next register. 

addressing the 

module for write 

transfer 

write transfers 

free slave address data byte data byte data byte data byte ... free 

register 

address 

a 

from master to module 

data for 

register 

with the 

register 

address 

a 

Figure 9 Writing into registers of the transceiver module 

data for 

register 

with the 

register 

address 

a+1 

data for 

register 

with the 

register 

address 

a+2 

The master can specify a register address with a write transfer of one data byte only: it is the register 

address. A subsequent read transfer will read out data; it will start with the specified register address (Figure 

10). 


module for write 

transfer 

free slave address data byte 


module for read 

transfer 

slave address 

from master to module 

from module to master 

write 

transfer 

register 

address 

a 

data byte data byte data byte data byte ... free 

data from 

register 

with the 

register 

address 

a 

data from 

register 

with the 

register 

address 

a+1 

Figure 10 Reading out registers of the transceiver module 

read transfers 

data from 

register 

with the 

register 

address 

a+2 

data from 

register 

with the 

register 

address 

a+3 

... 

... 

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After a reset the register address pointer is initialized with 0x00 (specifies the RX_MODE register, see below). 

If the register address pointer points beyond the highest defined register address, behavior on read and write 

attempts is undetermined. 

The transceiver module is always able to process start conditions and I 2 C addresses on the I 2 C bus, even 

though it processes any Easywave telegram internally. If the transceiver module is busy, it will slow down or 

stop the transfer on the I 2 C-bus for short time intervals after it has been addressed by a master. 

The transceiver module's registers are configured as follows: 

Register 

Address 

Register Name Description of Register 

0x00 RX_MODE Rx Mode register. The RX_MODE register controls the mode of the 

transceiver module as long as it does not transmit an Easywave telegram. 

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The RX_MODE register is a read-write register; a write specifies the desired 

Rx mode of the module; a read supplies the current Rx mode of the 

module. 

The module enters the desired Rx mode immediately after the RX_MODE 

register has been written. 

One of the following values can be read or written: 

• 0x00 (PWD_RST) 

The module is in power down state after a reset. The module's 

transceiver is switched off. 

The / REQ output is asserted. 

(Please refer to “Initialization on Reset“ on page 19.) 

• 0x01 (PWD) 

The module is in power down state. The module's transceiver is 

switched off. 

The / REQ output is not asserted. 

(Please refer to “Initialization on Reset“ on page 19.) 

• 0x02 (RX_RQ) 

The module is in Receive Mode. When the module enters the Receive 

Mode, it switches on its transceiver and tries receiving Easywave 

telegrams. 

The / REQ output indicates whether the module has received Easywave 

telegrams, which can be read out via the I 2 C-bus subsequently. 

The / REQ output also indicates whether Easywave telegrams are over. 

When the module terminates the Receive Mode (because another 

value than RX_RQ is written into the RX_MODE register), the module 

switches its transceiver on or off according to the desired mode. 

(Please refer to “Receiving of Easywave Telegrams“ on page 19.) 

• 0x03 (RX_PL) 

The module is in Receive Mode just as with the RX_RQ mode value, but 

the / REQ output always remains inactive. Polling of the RX_STATUS 

register is the only way of determining whether the module has 

received Easywave telegrams, which can be read out via the I 2 C-bus. 

When the module terminates the Receive Mode (because another 

value than RX_PL is written into the RX_MODE register), the module 

switches its transceiver on or off according to the desired mode. 

(Please refer to “Receiving of Easywave Telegrams“ on page 19.)


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Register 

Address 


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• 0x04 (LN_RQ) 

The module is in Learn Mode. When the module enters the Learn 

Mode, it switches on its transceiver and tries receiving Easywave 

telegrams. The module learns the first Easywave telegram which it 

receives. 

The / REQ output indicates whether the module has received and 

learned an Easywave telegram. 

When the module terminates the Learn Mode (because another value 

than LN_RQ is written into the RX_MODE register), the module switches 

its transceiver on or off according to the desired mode. 

(Please refer to “Learning of Easywave Telegrams“ on page 21.) 

• 0x05 (LN_PL) 

The module is in Learn Mode just as with the LN_RQ mode value, but 

the / REQ output always remains inactive. Polling of the RX_STATUS 

register is the only way of determining whether the module has 

received and learned an Easywave telegram. 

When the module terminates the Learn Mode (because another value 

than LN_PL is written into the RX_MODE register), the module switches 

its transceiver on or off according to the desired mode. 

(Please refer to “Learning of Easywave Telegrams“ on page 21.) 

• 0x06 (DELLN) 

The module's transceiver is switched off. The module deletes a learned 

Easywave telegram. 

The / REQ output is not asserted. 

(Please refer to “Delete Learned Easywave Telegrams“ on page 22.) 

0x01 RX_STATUS Rx Status register. This register indicates received and learned Easywave 

telegrams while being in Rx mode or Learn mode. 

The RX_STATUS register is a read-only register, a write to the register has 

not any effect. 

• Bit 7: (RX_TEL_CHANGED) 

The RX_TEL_CHANGED bit is set to 1 if the received Easywave 

telegram changes while being in Receive Mode: An Easywave telegram 

has received or an Easywave telegram has been received which differs 

from the preceding one or there is not any further valid Easywave 

telegram received. 

If the RX_TEL_CHANGED bit is set from 0 to 1, the transceiver module 

sets the RX_CHANNEL and RX_BUTTON registers, and the 

RX_TEL_VALID bit in this Rx Status register according to the received 


While the RX_TEL_CHANGED bit is 1, the RX_CHANNEL and 

RX_BUTTON registers and the RX_TEL_VALID bit in this Rx Status 

register won't change their contents even if another Easywave telegram 

is received. 

Reading the RX_ACK register clears the RX_TEL_CHANGED bit. 

(Please refer to “Receiving of Easywave Telegrams“ on page 19.)


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Register 

Address 


7007 

• Bit 6: (RX_TEL_VALID) 

The RX_TEL_VALID bit is set or cleared if the received Easywave 

telegram changes while being in Receive Mode. If an Easywave 

telegram has been recived which differs from the preceding one, the 

RX_TEL_VALID bit is set to 1. If there is not any further valid 

Easywave telegram received, the RX_TEL_VALID bit is set to 0. 

The RX_TEL_VALID bit is used together with the RX_TEL_CHANGED 

bit. (Please refer to “Receiving of Easywave Telegrams“ on page 19.) 

0x02 RX_CHANNEL Rx Channel register. It specifies the channel number (0...31) while 

receiving or learning of an Easywave telegram, or while deleting of a 

learned Easywave telegram. 

The RX_CHANNEL register changes its content upon receiving of an 


The RX_CHANNEL register also specifies what channel's user data the 

RX_USERDATA0 and RX_USERDATA1 registers map. 

The RX_CHANNEL register is a read-write register. 

(Please refer to “Receiving of Easywave Telegrams“ on page 19, 

“Learning of Easywave Telegrams“ on page 21, and “Delete Learned 

Easywave Telegrams“ on page 22.) 

0x03 RX_BUTTON Rx Button register. It specifies the button number while receiving or 

learning of an Easywave telegram. 

The RX_CHANNEL register is a read-write register; a write to the 

RX_CHANNEL register modifies the register's content, but has not any other 

effect. 


• 0x00 Easywave Button A (“On“ or “Up“); 

• 0x01 Easywave Button B (“Off“ or “Down“); 

• 0x02 Easywave Button C (“Stop“); 

• 0x03 Easywave Button D (“Stop“) 

(Please refer to “Receiving of Easywave Telegrams“ on page 19, 

“Learning of Easywave Telegrams“ on page 21, and “Delete Learned 


0x04 RX_USERDATA0 Rx User Data Byte#0 register. The RX_USERDATA0 register maps an 

opaque user data byte here which the transceiver module stores 

associated with each channel. 

The I 2 C master can store some data here. Since the RX_CHANNEL register 

contains the channel number of a received Easywave telegram, the 

RX_USERDATA0 register automatically maps the user data byte value 

which is associated with the received Easywave telegram. 

The RX_USERDATA0 register is a read-write register. 

The transceiver module stores the user data bytes in persistent storage. 

Note that the current implementation interrupts any receive attempts of 

Easywave telegrams while the persistent storage is written.


Index 1.01 

Project No. 


Development 


Register 

Address 


0x05 RX_USERDATA1 Rx User Data Byte#1 register. 

7007 

It works just as the RX_USERDATA0 register, but holds another opaque 

user data byte. 

0x06 RX_ACK Acknowledges a change of received Easywave telegrams while being in 

Receive mode or Learn mode. 

A read access to the RX_ACK register clears the RX_TEL_CHANGED bit in 

the RX_STATUS register. (Please refer to “Receiving of Easywave 

Telegrams“ on page 19.) 

A read access to the RX_ACK register supplies 0x00. 

A write access to the RX_ACK register has not any effect. 

0x10 TX_STATUS Tx Status register. This register indicates transmission of Easywave 

telegrams. 

The TX_STATUS register is a read-only register, a write to the register has 

not any effect. 

• Bit 7: (TX_TRANSMIT) 

The TX_TRANSMIT bit is set to 1 if the transceiver module transmits 

Easywave telegrams. (Please refer to “Transmitting of Easywave 

Telegrams“ on page 22.) 

0x11 TX_CHANNEL Tx Channel register. It specifies the channel number (0...31) of an 

Easywave telegram, which the transceiver module should transmit. 

The TX_CHANNEL register is a read-write register. 

(Please refer to “Transmitting of Easywave Telegrams“ on page 22.) 

0x12 TX_BUTTON Tx Button register. It specifies the button number of an Easywave 

telegram, which the transceiver module should transmit. 

The TX_CHANNEL register is a read-write register. 


• 0x00 Easywave Button A (“On“ or “Up“); 

• 0x01 Easywave Button B (“Off“ or “Down“); 

• 0x02 Easywave Button C (“Stop“); 

• 0x03 Easywave Button D (“Stop“) 

(Please refer to “Transmitting of Easywave Telegrams“ on page 22.) 

0x13 TX_ACK Acknowledges an Easywave telegram which the transceiver module 

should transmit. 

A write access to the TX_ACK initiates transmitting of an Easywave 

telegram with the channel of the TX_CHANNEL register and the button 

number of the TX_BUTTON register. (Please refer to “Transmitting of 


A read access to the TX_ACK register supplies 0x00 and has not any 

effect.


Index 1.01 

Project No. 


Development 


Register 

Address 


0x20 RX_LN_CH0_7 A bit mask that indicates whether a channel has learned an Easywave 

telegram (receive). 

7007 

A bit for the specific channel is set to 1 upon learning an Easywave 

telegram (LN_RQ and LN_PL value of the RX_MODE register, please refer 

to “Learning of Easywave Telegrams“ on page 21.) 

A specific bit is cleared upon deletion of a learned Easywave telegram 

(DELLN value of the RX_MODE register, please refer to “Delete Learned 


Any bit is cleared when ELDAT ships the transceiver module RTRM08. 

• Bit 0: Channel 0 (channel number of the RX_CHANNEL register); 







• Bit 7: Channel 7 (channel number of the RX_CHANNEL register) 

0x21 RX_LN_CH8_15 Just as the RX_LN_CH0_7 register, but for channels 8 to 15. 

















• Bit 7: Channel 23 (channel number of the RX_CHANNEL register)


Index 1.01 

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Register 

Address 



Initialization on Reset 

7007 









After a reset the transceiver module is in power down state, and the transceiver is switched off. 

The / REQ output is low. 

The RX_MODE register is set to the PWD_RST value. 

The I 2 C master can set the RX_MODE register to the PWD value; the / REQ output goes high then. 

The PWD_RST mode is intended to recognize an occurred reset (due to a malfunction or a power fail) by the 

asserted / REQ output. 

Receiving of Easywave Telegrams 

The RX_MODE register must be set to the RX_RQ value or the RX_PL value (Recevive Mode). If the RX_MODE 

register is RX_PL, the / REQ output is always inactive (high). If the RX_MODE register is set to RX_RQ, the 

/ REQ output works as described in the next paragraphs. 

The transceiver module maintains learned telegrams. Each learned telegram is associated with a channel. 

There are 32 channels. A channel can store one learned Easywave telegram (the channel is used) or a 

channel stores not any learned Easywave telegram (the channel is unused). 

There is a bit mask in the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31 

registers which indicates usage of each channel (a channel is used or unused). 

The transceiver module ignores a received Easywave telegram if it isn't equal to any of the learned Easywave 

telegrams. 

The / REQ output is high at first, the RX_TEL_CHANGED-bit in the RX_STATUS register is 0 (Figure 11). 

The module switches on its transceiver and tries receiving some Easywave telegrams. When the module 

receives an Easywave telegram, it does the following (Figure 11): 

• The / REQ output goes low, and the RX_TEL_CHANGED-bit in the RX_STATUS register is set to 1 upon one 

of the following conditions: 

• The module has started receiving an Easywave telegram which is a learned one (after a pause or 

after a preceding Easywave telegram). The RX_TEL_VALID-bit in the RX_STATUS register is set 

to 1; it indicates the begin of a new Easywave telegram. (For example the user has pushed a 

button of a transmitter.) The RX_CHANNEL register and the RX_BUTTON register contain the 

channel number (of the learned Easywave telegram) and the button number. The RX_USERDATA0


Index 1.01 

Project No. 


Development 


7007 

and RX_USERDATA1 registers contain the opaque user data which is associated with the channel 

number. 

• The module does not receive further valid learned Easywave telegrams. The RX_TEL_VALID-bit 

in the RX_STATUS register is set to 0 now; it indicates the end of a learned Easywave telegram. 

(For example, the user has released the button of a transmitter.) 

• The I 2 C master can read out the channel number, the button number, and the opaque user data if the 

RX_TEL_VALID-bit in the RX_STATUS register is 1. 

While the RX_TEL_CHANGED bit is 1, the transceiver module won't change the contents of the 

RX_CHANNEL and RX_BUTTON registers and of the RX_TEL_VALID bit in the RX_STATUS register even if 

another Easywave telegram is received. 

• If the I 2 C master reads the RX_ACK register, the transceiver module drops the channel number and the 

button number of the received telegram. The RX_ACK register also can be read in a single read transfer 

with the other registers mentioned above. If one of the above conditions has occurred meanwhile, the 

/ REQ output remains low, and the RX_TEL_CHANGED-bit in the RX_STATUS register remains 1. Otherwise 

the transceiver module clears the RX_TEL_CHANGED-bit in the RX_STATUS register and the / REQ output 

goes high. (For example, a user holds down the button of a transmitter or the user does not push any 

button.) If the / REQ output goes high, the transceiver module guarantees that it happens before the I 2 C 

read transfer from the RX_ACK register on the I 2 C-bus terminates. 

The green LED blinks as long as the transceiver module receives any Easywave telegram. (The LED is 

drawn on Figure 1 on page 4). 

transceiver 

/REQ 

output 

RX_TEL_- 

CHANGED 

RX_TEL_- 

VALID 

I 2 C-bus 

high 

low 

1 

0 

1 

0 

RX 

on 

receive 

telegrams #1 

read 

data: 

begin 

telegr. 

#1 

RX 

on 

read 

data: 

end of 

telegr. 

Figure 11 Sequence when receiving Easywave telegrams 

receive 

telegrams #2 

read 

data: 

begin 

telegr. 

#2 

receive 

telegrams #3 

read 

data: 

begin 

telegr. 

#3 

RX 

on 

read 

data: 

end of 

telegr. 

A master should perfom the following steps if it wants to receive Easywave telegrams subsequent it has set 

the RX_MODE-register to the RX_RQ or RX_PL value: 

• Wait until the / REQ output goes low (RX_RQ only) or wait until the RX_TEL_CHANGED-bit in the


Index 1.01 

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7007 

RX_STATUS register is 1. Check the RX_MODE register. If the RX_MODE register is PWD_RST, set the 

RX_MODE register to RX_RQ or RX_PL again, and start with the first bullet. 

• Read the RX_TEL_VALID-bit in the RX_STATUS register, the channel number, the button number, and the 

opaque user data from the RX_CHANNEL, RX_BUTTON, RX_USERDATA0, and RX_USERDATA1 registers if 

necessary. 

• Read the RX_ACK register. 

• Start with the first step. 

Note that the current implementation interrupts any receive attempts of Easywave telegrams while the 

RX_USERDATA0 and RX_USERDATA1 registers are written. 

Learning of Easywave Telegrams 

The RX_MODE register must be set to the LN_RQ value or the LN_PL value (Learn Mode). If the RX_MODE 

register is LN_PL, the / REQ output is always inactive (high). If the RX_MODE register is set to LN_RQ, the 

/ REQ output works as described in the next paragraphs. 

The Learn Mode works just as the receive mode except that the transceiver module does not modify the 

RX_CHANNEL register. The I 2 C master has to set this register appropriately and the transceiver module 

learns the first Easywave telegram which it receives after entering the Learn Mode. 

The transceiver module ignores any received Easywave telegram while being in Learn Mode if it is one which 

has been already learned before. 

After the transceiver module has learned an Easywave telegram, it ignores further received Easywave 

telegrams. 

The transceiver module sets the appropriate bit in the bit mask of the RX_LN_CH0_7, RX_LN_CH8_15, 

RX_LN_CH16_23, and RX_LN_CH24_31 registers to indicate that the channel is used now. If the channel 

has been used before, the Easywave telegram which has been learned before will be overwritten. 

The green LED blinks as long as the transceiver module receives any Easywave telegram. (The LED is 

drawn on Figure 1 on page 4). 

A master should perfom the following steps if it wants to learn an Easywave telegram: 

• Set the RX_MODE register to the PWD or PWD_RST value. This prevents the transceiver module from 

modifying the RX_CHANNEL register. 

• Set the RX_CHANNEL register appropriately. The master can determine an unused channel by reading the 

bit mask from the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31 registers. 

The master also can write some user data into the RX_USERDATA0 and RX_USERDATA1 registers. 

• Set the RX_MODE register to the LN_RQ or LN_PL value. 

• Wait until the / REQ output goes low (LN_RQ only) or wait until the RX_TEL_CHANGED-bit in the 

RX_STATUS register is 1. Check the RX_MODE register. If the RX_MODE register is PWD_RST, start with the 

first bullet. 

• Read the RX_TEL_VALID-bit in the RX_STATUS register, the channel number, the button number from 

the RX_CHANNEL and RX_BUTTON registers if necessary. 

• Read the RX_ACK register. 

• If the RX_TEL_VALID-bit in the RX_STATUS register was 1 above, the transceiver module has learned an 

Easywave telegram. If the RX_TEL_VALID-bit in the RX_STATUS register was 0, the master should 

continue waiting for an Easywave telegram (fourth bullet). 

• The master can write some user data into the RX_USERDATA0, and RX_USERDATA1 registers again if 

desired.


Index 1.01 

Project No. 


Development 


The master can abort the procedure before an Easywave telegram is learned by setting the RX_MODE 

register to any value unequal to the LN_RQ or LN_PL value. 

Delete Learned Easywave Telegrams 

The RX_MODE register must be set to the DELLN value. The / REQ output is always inactive (high). 

When the DELLN value is written into RX_MODE register, the transceiver module immediately deletes the 

learned Easywave telegram of the channel which is specified by the RX_CHANNEL register. 

The transceiver module clears the appropriate bit in the bit mask of the RX_LN_CH0_7, RX_LN_CH8_15, 

RX_LN_CH16_23, and RX_LN_CH24_31 registers to indicate that the channel is no longer used. If the 

channel was not used before, the entire procedure described in this paragraph has not any effect. 

A master should perfom the following steps if it wants to delete a learned Easywave telegram: 

• Set the RX_MODE register to the PWD or PWD_RST value. This prevents the transceiver module from 

modifying the RX_CHANNEL register. 

• Set the RX_CHANNEL register appropriately. The master can determine an used channel by reading the bit 

mask from the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31 registers. 

• Set the RX_MODE register to the DELLN value. 

Transmitting of Easywave Telegrams 

The transceiver module has 32 built-in Easywave telegrams which it can transmit. 

A write access to the TX_ACK register initiates transmitting of an Easywave telegram with the channel of the 

TX_CHANNEL register and the button number of the TX_BUTTON register. The TX_ACK register also can be 

written in a single write transfer with the other mentioned registers. The transceiver module does the 

following: 

• The transceiver module switches its transceiver on and transmits a fixed count of Easywave telegrams 

regardless of the content of the RX_MODE register. The / REQ output and the status bits in the RX_STATUS 

register remain on their state. As long as the transceiver transmits, the TX_TRANSMIT-bit in the 

TX_STATUS register is 1. While the transceiver transmits, further writes into the TX_ACK register have not 

any effect. The master has to check the TX_TRANSMIT-bit in the TX_STATUS register whether it can 

initiate a desired transmission of a further Easywave telegram. 

• When the transceiver has finished transmitting of telegrams, it switches its transceiver on (receive) or off 

according to the RX_MODE register and continues operation as specified by the RX_MODE register. The 

TX_TRANSMIT-bit in the TX_STATUS register is 0 now. 

The yellow LED lights as long as the transceiver transmits. (The LED is drawn on Figure 1 on page 4). 

7007


Index 1.01 

Project No. 


Development 


I 2 C-bus 

TX_TRANSMIT 1 

0 

transceiver 

write 

data: 

telegr. 

#1 

transmit 

telegrams #1 

Figure 12 Sequence when transmitting Easywave telegrams 

write 

data: 

telegr. 

#2 

transmit 

telegrams #2 

A master should perfom the following steps if it wants to transmit Easywave telegrams: 

• Check the TX_TRANSMIT-bit in the TX_STATUS register and wait until it is cleared. 

• Write the desired channel number and button number into the TX_CHANNEL and TX_BUTTON registers. 

• Write any value into the TX_ACK register. 

• Start with the first step for the next Easywave telegram. 

3 Electrical Characteristics 

3.1 Absolute Maximum Ratings 

7007 

Absolute Maximum Ratings Min Max Units 

Voltage V CC on VCC pin with respect to GND -0.3 5.8 V 

Voltage on any pin with respect to GND -0.3 V CC + 0.3 V 

Input clamp current and output clamp current - +/-20 mA 

Maximum output current by any output - +/-25 mA 

Ambient temperature under bias -40 85 °C 

Storage temperature -40 125 °C 

3.2 Operating Conditions 

Operating Conditions Min Max Units Conditions 

Supply voltage V CC 2.1 5.25 V


Index 1.01 

Project No. 


Development 


7007 

Operating Conditions Min Max Units Conditions 

Input low voltage 0 0.8 V 4.5 V


Index 1.01 

Project No. 


Development 


7007 

Characteristics Min Typ Max Units Conditions 

Supply current while powered down - 2.2 µA 25°C, 

V CC = 3 V 

Supply current while powered down when a start 

condition and an I 2 C-address is on the I 2 C-bus 

Frequency of carrier 868.3 MHz +/- 50 kHz 

Output power (whip antenna) +2 

- 3.4 µA 25°C, 

V CC = 5 V 

- 7.5 µA 85°C, 

V CC = 3 V 

- 10.8 µA 85°C, 

V CC = 5 V 

- 1.0 mA V CC = 3 V 

- 1.7 mA V CC = 5 V 

+5 

dBm 

dBm 

V CC = 2.1 V 

V CC = 3 V 

+9 dBm V CC = 5 V 

Receiver sensitivity (whip antenna) -105 dBm 

Approval standards EN 300 220-1 V1.3.1 (2000-09) 

EN 300 220-3 V1.1.1 (2000-09) 

4 Mechanical Specification 

Please refer to Figure 13. 

Use the 

transceiver 

module with 

the supplied 

antenna.


Index 1.01 

Project No. 


Development 


2.54 

39 

30.48 

Figure 13 Drawing of the transceiver module 

17.96 

21.76 

3.5 max 

1.6 

7007 

equipped 

components

Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

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