The IC Package

FEBRUARY 2006
THE INTERNATIONAL MAGAZINE FOR ELECTRONIC PACKAGING APPLICATIONS
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Providing the Missing Link
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Measuring 3-D Packages
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www.apmag.com
Copyright by PennWell Corporation

The IC Package
Cover Image
courtesy of
Cadence Design Systems
MISSING LINK BETWEEN NANOMETER SILICON AND MULTI-GIGABIT PCB SYSTEMS
BY AN-YU KUO AND ZHEN MU
As nanometer-scale ICs become
commonplace andprinted
circuit board (PCB)
system data rates achieve
multi-gigabit levels, it is increasingly
important for designers to consider the
entire system interconnect — from IC
to package to board to package. From
this vantage point, IC package design
takes on new importance. It becomes
the critical link in the signal and power
paths where money and time are
gained or lost.
In the face of this pressure, highspeed
IC package designers must ensure
both signal and power integrity
by making certain IC package structures
are properly modeled, extracted,
and simulated with the rest of the circuit
on both signal and power delivery
paths. Fortunately, integrated modeling
and analysis techniques and tools
are available to describe a complicated
package structure with true 3-D representations,
and simulate those representations
in the context of system
interconnect. These tools help designers
consider the package effect from
designs and make decisions based on
actual conditions, thus reducing design
iterations, cycles, and development
time.
3-D Modeling
As modeling is an integral part of the
design and analysis of IC packages, it
is important to look at the options. For
the past two decades, 2-D field solvers
have been used successfully for
modeling traces on PCBs. However,
increasing package complexity and
density has resulted in signal traces
with more vias, segments, and discontinuities.
Complex packages place
traces on many layers. Package-interconnect
elements, such as nonorthogonal
traces, vias, wire bonds, and solder
balls must be modeled. As 2-D field
solvers cannot address 3-D behaviors,
3-D solutions have to be used. There
are two types of complementary 3-D
field solvers — full-wave and quasistatic
— that are useful in representing
package behavior, depending on
the application. Both can be used in
conjunction with 2-D solvers.
As illustrated in Figure 1, signals
propagate in a simple transverse electromagnetic
(TEM) mode on long
transmission lines. For these designs,
traditional 2-D field solvers are
accurate enough and much faster than
3-D field solvers. However, Figure 2
shows how signal propagation modes
in packages require a 3-D field solver.
Quasi-static and Full-wave
Field Solvers
Quasi-static field solvers are used when
signals traveling on conductive paths
have lower speeds — usually data
rates below 5 Gbps. Quasi-static solvers
produce field solutions by ignoring
the displacement current. With such
simplification, electrical fields remain
static outside conductors, but magnetic
fields retain frequency dependency
inside conductors so that the skin effect
can be accounted for properly.
Capacitance (C) and conductance (G)
of a structure are determined by electrical
fields only; resistance (R) and
Photo courtesy of Amkor Technologies, Inc.

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0
Figure 1. Electrical field distribution on a long differential pair.
inductance (L) are determined only by
magnetic 0602apKuof1 fields. In other words, by ignoring
the displacement current, magnetic
and electrical
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fields are decoupled
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in the quasi-static
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theory, and can be
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solved independently.
Because of the
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decoupling between
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electrical and magnetic
fields, a qua-
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si-static field solver 55443.4
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is quicker and can
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solve much bigger
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problems than a fullwave
solver. Many 9240.6
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0
modern quasi-static
solvers can perform
whole-package
RLGC extraction of a complicated
package design in a few hours.
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Most designers wonder about the
highest frequency at which the quasistatic
assumption is still valid. While it
is difficult to provide a universal upper
limit to the applicability of quasi-static
solvers, in high-speed package designs, 3
to 4 GHz is an acceptable value.
Full-wave field solvers are used in cases
where strong electromagnetic coupling,
resonance, and radiation require
accurate solutions of Maxwell equations.
A full-wave field solver is capable
of solving Maxwell equations at any
given frequency. It solves electrical and
magnetic fields together so that the interaction
between electrical and magnetic
fields is handled properly. As a result,
this type of solver can take into account
displacement currents,
electromagnetic
radiation, and
field coupling. Because
there are limits
in computer capacities,
full-wave field
solvers are best applied
to obtain solutions
of small geometries;
for example,
z coupled critical signal
traces carrying
y
x 12.5-Gbps signals.
In practice, designers
will use 3-D field
solvers in addition to
2-D solvers. While the choice of field solvers
is application-dependent, any field
solver must be integrated into a design
Figure 2. Electrical field distribution of a package model.
Integrating Packaging Effects 0602apKuof3 in
z
I/O
driver
system that enables engineers
to explore, design,
implement, and
verify interconnect topologies
and electrical
constraints through
simulation. Such an integrated
environment
can eliminate time
wasted in translations
and re-entering of design
data, in addition to ensuring product
performance.
x
y
RC model
of RDL
Represent
RDL from IC tool
High-Speed Design
Today’s high-speed digital systems are
characterized by high current capacity,
high data rates, and low voltage,
forcing design focus on power delivery.
The challenge of providing sufficient
and stable power to active devices
through PCBs and packages
elevates power delivery design to the
system level. To solve the problem,
the IC, package, and board must be
considered.
To illustrate how designers can use 3-
D package representations and efficiently
simulate those representations within a
cross-domain environment, an example
demonstrates addressing signal delays by
modeling package interconnects with a
quasi-static 3-D field solver, and by simulating
the entire signal paths from output
buffers to input buffers. This differs
from the typical current flow/methodology
where the power supply to the IC
core is assumed ideal, or at best, attenuated
by a lumped, fixed-impedance, approximated
load meant to represent the
IC package and the PCB.
Figure 3 shows the die-to-die signal path
and highlights the importance of working
in an integrated design and analysis environment
that allows for cross-domain
communication. It is a virtual or abstract
system interconnect model (VSIC), which
enables complete modeling and analysis
of the interconnect across silicon, package,
and PCB. The redistribution layer
(RDL) model is drawn from the IC database,
the package parasitics from the IC
package tool, and the board trace models
from the PCB layout tool.
Figure 4 provides a look at the simulation
flow for the same circuit within
3-D model extraction
for package parasitics
Package
parasitics
RDL and package
repeating here
(ignored)
I/O
receiver
Trace model
on board
2-D model of
traces on board
Figure 3. VSIC model of a buffer-to-buffer interconnect pathway.
the design and analysis environment.
Following the simulation flow, a net
on the design can be modeled in three
pieces: the RDL equivalent model, the
3-D package model, and the 2-D board
trace model. By simulating the extracted
circuit, signal distortion and delay
between output buffer and input buffer
can be measured.

C O V E R S T O R Y
Driver I/O:
model
Receiver I/O:
model
Integrated design and analysis environment
Package layout file
3-D package
model extraction
(RLGC, S-parameter)
Simulating signal path
(single or coupled)
Measure and report
signal degradation,
crosstalk, and delays
from die pad to board
through package
To ensure power integrity, two fundamental
design requirements must be
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met. Sufficient supply voltage and current
must be delivered from the battery to ICs
through PCBs and packages, and the supply
must be kept clean and stable during
the operating range of the device.
Sufficient power supply to the IC core
circuitry demands a low impedance
path for the entire power delivery network,
while the stability of supply voltages
requires the power delivery network
to have the desired level of noise
immunity induced by simultaneous
switching of high-speed signals during
device/system operation. If a low-impedance
path for a power delivery network
can be maintained, then a stable
power supply should be achieved easily.
Easier said than done? Not if this oftenoverlooked
missing link is taken into
consideration — the successful provision
and maintenance of a low-impedance
path for the power supply at the
frequency range of interest.
PCB interconnects,
load information
RDL RC model
Figure 4. An integrated environment provides a complete solution for
system-level timing analysis.
Providing sufficient
and stable power to
active devices through
PCBs and packages
elevates power
delivery design to the
system level.
To create an ideal
low-impedance
path, an effective
plane configuration
on the PCB and corresponding
power
and ground net
structures on the IC
package is used. If
the target low impedance
cannot be
achieved, a decoupling
strategy must
be used. Although
the design of a lowimpedance
path can
be achieved using
frequency-domain
simulation, the final
power supply network should be
verified in the time domain to see how
much power has been lost through the
PCB and package, and if the power supply
variation (voltage
ripple) is controlled
within a certain budget
when noise is injected
into the power
supply network.
Both the design
and verification
phases can be
achieved by modeling
each element of
y
z
the power delivery x
path and performing
an overall simulation
of the entire quasi-static field solver.
path. Because of the
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geometric complexity of the power and
ground nets in an IC package, and the
overwhelming circuit size of the power
grid in an IC, one simulation tool can
not be expected to simulate the entire
power and ground paths. Therefore, it is
essential to use integrated flow of simulation
tools that support either IC, package,
or board-level simulation.
Key to making this methodology viable
is the adoption of an integrated
co-design methodology between the
IC core and package design. By using
a co-design process, the actual IC dieto-package
interfaces (IC-core, verilog
port names and IC-package, die-footprint
bump names) can be mapped and
used for building a complete power and
ground network from voltage source to
IC die; including the intermediate IC
package model, which is modeled as a
true 3-D quasi-static model. This power
and ground supply network 3-D model
of the IC package (Figure 5) is connected
to the power grid on the IC core, enabling
dynamic IR-drop simulation.
In real design cases, worst-case IR-drop
can be 20% higher when package effects
are included in the IR-drop simulation
than when they’re not. Therefore, by using
a methodology that allows for IC
package co-design and analysis, more accurate
results are achievable, and a rightfirst-time
tapeout for both the IC and the
IC package is possible.
Figure 5. 3-D model of the power and ground networks created by a
Conclusion
High-speed system design must consider
IC package effects to alleviate SI and
power delivery problems of final
assembled devices. Both fullwave
and quasi-static field solvers
are needed to represent package
behavior. Despite common belief,
2- and 3-D field solvers are complementary
to each other in targeting different
applications. A simulation environment
with integrated field solvers is essential
in providing complete signal integrity
and power delivery solutions for highspeed
IC/package and PCB designs. AP
AN-YU KUO, Ph.D., CTO, may be contacted at
Optimal Corp., 6980 Santa Teresa Blvd., Suite 100,
San Jose, CA 95119-1346; 408/363-6300; E-mail:
aykuo@optimalcorp.com. ZHEN MU, Ph.D., senior
technologist, may be contact at Cadence Design
Systems Inc., 2655 Seely Ave., San Jose, CA 95134;
408/943-1234; E-mail: zhenm@cadence.com.