Vertically Integrated Test/Calibration and Reliability Enhancement ...

Vertically Integrated
Test/Calibration and Reliability
Enhancement for Systems with
RF/Analog Content
Sule Ozev
Sule.ozev@asu.edu
(480) 727 7547
Arizona State University
School of Electrical, Computer, and
Energy Engineering
1

Outline
• Trends and challenges they bring
• Post production calibration with a global
view
• Defect-based screening
• Reliability modeling issues and reliability
enhancement
• Vision
2

Trends
• Integration of digital, analog, RF
subsystems
• Increasing process variations
• Increasing defect rates
• Reducing mean-time-to-failure
• Continuous optimization of processes for
digital performance
• Increasing digital processing capability
3

Challenges for Analog/RF Circuits
• Process variations introduce uncertainty into
performance
– Post-production calibration is necessary not just of
high-resolution operations, but for all functionalities
• Increasing defectivity requires defect-based
screening techniques
– Screening techniques need to be analyzed in terms of
defect coverage
• Continuous process optimization
– Learned behavior and/or correlations need to be
revised through product lifetime
• Reducing lifetime
– Analog/RF subsystems may become single points of
failure 4

Post-production Calibration
• Analog designers have been dealing with process
variations
– Many specific techniques exist to calibrate
performance to within specifications
• ADCs, PLLs
– Few generally applicable techniques exist
• Bias tuning with bias banks or DC voltage control
• Bias tuning with negative feedback
• Frequency tuning with banks of passive devices or voltage
controlled passives
• Adjustment of matching networks with capacitor tuning
• Adjustment of transistor width
• Trade-offs almost always exist
– Tuning for one performance parameter may degrade
another one
– e.g. gain vs. linearity or linearity vs. power
consumption
5

Calibration in the Context of
Complex Systems
• System is made up of many blocks,
compensation effects need to be taken
into account
Block X
Block Y
G Y_min = 9dB
G Y_max =11dB
G X_min = 9dB
G X_max =11dB
G min =18dB
G max =22dB
G Y =7dB
G X =11dB
G=18dB
• Local calibration may not always produce
optimum results
G Y =7dB
G X=10dB
G=17dB
G Y =8dB
G X =10dB
G=18dB
G Y =7dB
G X =11dB
G=18dB
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Digital Processing
• With millions of transistors available, digital
processing capability increases
• Digital compensation becomes more affordable
• Examples of digital compensation exist
– e.g. pipelined ADCs
– e.g. Compensation of IQ mismatch in transceivers
• Well, it is not free!
– Processing capability is there but it most certainly has
other uses
• Computational overhead of compensation
– Digital circuits are slow
• Latency of compensation
– Any additional operation adds power consumption
• Yet another power/performance trade-off
7

Calibration in the Context of
Complex Systems
• Local calibration needs to work in
conjunction with system-level optimization
– Trade-offs of each calibration scheme
– Trade-offs at the system level
– Trade-offs and limits of digital compensation
– Optimization process that decides what level
of calibration and/or compensation
8

Increasing Defectivity
• Use of high-end digital processes for
analog/RF circuits introduces higher
defectivity
– Hard defects
– Parametric deviations beyond process
tolerance
9

Defect Manifestation
Defects
Physical
Phenomena
Catastrophic
Faults
Parametric
Faults
Circuit
Manifestations
Specification
Violation
Acceptable
Specifications
Effect on
Specifications
• Most physical defects will result in complete loss of
functionality
– e.g. most open-circuit or short circuit defects that fall in the
signal path
• Some defects result in a shift in the overall behavior
– e.g. broken finger of a transistor
– e.g. inductor coil shorts

How do defects affect the test
process
• Traditional specification-based testing
– If all specifications are measured, then there is no problem
with initial quality
– Almost certainly will not be the case
– Test selection is typically y based on learned statistical
information
– Defective circuits do not follow the statistics
– Defect-based selection techniques are needed
• New techniques for testing
– Techniques that rely on the measurement of correlated
parameters (e.g. bias current, or DC voltages)
– Techniques developed for BIST applications (e.g. sensorbased
testing)
– Techniques that rely on correlations among specifications
(e.g. machine-learning i based testing) ti – … need to be evaluated for defect response 11

Continuous Process Optimization
• Conclusions drawn from early samples
(characterization data) may not be valid
later on
• Adaptive test/calibration techniques are
needed
– Re-learn through h process shifts
– Mechanisms of learning need to be
continuously refined
12

Reliability
• Not much attention has been paid to
analog/RF circuit reliability
• Device reliability has been extensively
studied
– E.g. electromigration, oxide breakdown
– Some research still needed for other analog
components (inductors, capacitors)
• Existing i aging models are generally based
on digital circuits
13

Analog Circuit Wearout vs. Digital
Circuit Wearout
• Using models and techniques from the
digital domain is a start
• However, wearout patterns may be
significantly different
– constant t bias vs. smaller stress on Vgs
• Does this suggest electromigration is more of an
issue than oxide breakdown?
– Wearout is not uniform
• e.g. RF choke in a power amplifier vs. input
inductor in an LNA
14

Analog/RF Reliability
• Wearout monitors are needed
– Local monitors
• Bottom-up approach
• Duplicating the operating conditions on critical
components may be too costly (area, power)
• Diagnosis is easy but monitoring is hard
– System-level monitors with local diagnosis
• Top-down approach
• Analog diagnosis is very challenging but possible
• Monitoring i is easy but diagnosis i is challenging
15

Reliability Enhancement
• Handle degradation in performance at the
system level (compensation)
• Re-calibrate at the circuit-level
• Replace degraded unit
• Same issues?
16

Re-calibrating for Reliability
Enhancement
• Can we use the same post-production
p
calibration schemes?
• Sometimes, but not always
– Calibration schemes may be counter-productive
ti
for reliability
– e.g. LNA
• Degradation of inductor reduced gain increase
bias current faster degradation
• Need to perform system-level trade-off
analysis
– e.g. can we off-load some of the work of the
degraded building block to another building
block?
17

Replacement/Reconfiguration
• If degradation is beyond a certain level,
replacement is needed
• Replacement of complete functionality is
optimal from performance perspective
– e.g. replace the complete receiver chain
– But, costly in terms of hardware
• Replacement at the lower levels is
possible
– Loading, noise injection
– How to turn off the component not being
used?
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Vision
• Research is needed at multiple levels of
hierarchy
– Circuit-level calibration
– System-level compensation using digital
computation
ti
– Defect-based testing and test evaluation
– Reliability monitoring
– Reliability enhancement
– Re-configuration
– Global optimization that takes all trade-offs into
account
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