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The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the<br />
main program and interrupt routines perform access to registers using TEMP, interrupts<br />
must be disabled during access from the main program (and from interrupt routines if<br />
interrupts are allowed from within interrupt routines).<br />
Timer/Counter1 in PWM Mode<br />
When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A<br />
(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,<br />
free-running, glitch-free and phase-correct PWM with outputs on the PD5(OC1A) and<br />
OC1B pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to<br />
TOP (see Table 11), where it turns and counts down again to zero before the cycle is<br />
repeated. When the counter value matches the contents of the 10 least significant bits of<br />
OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set or cleared according to the settings<br />
of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control<br />
Register (TCCR1A). Refer to Table 12 for details.<br />
Table 11. Timer TOP Values and PWM Frequency<br />
PWM Resolution Timer TOP Value Frequency<br />
8-bit $00FF (255) f TCK1 /510<br />
9-bit $01FF (511) f TCK1 /1022<br />
10-bit $03FF(1023) f TCK1 /2046<br />
Table 12. Compare1 Mode Select in PWM Mode<br />
COM1X1 COM1X0 Effect on OCX1<br />
Note:<br />
0 0 Not connected<br />
0 1 Not connected<br />
1 0<br />
1 1<br />
X = A or B<br />
Cleared on compare match, up-counting. Set on compare match,<br />
down-counting (non-inverted PWM).<br />
Cleared on compare match, down-counting. Set on compare match,<br />
up-counting (inverted PWM).<br />
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,<br />
are transferred to a temporary location. They are latched when Timer/Counter1 reaches<br />
the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the<br />
event of an unsynchronized OCR1A/OCR1B write. See Figure 32 for an example.<br />
40 AT90S8515<br />
0841G–09/01