At90s8515 - Atmel Corporation

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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 2. Oscillator Connections MAX 1 HC BUFFER HC C2 C1 XTAL2 XTAL1 GND Note: When using the MCU oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. Figure 3. External Clock Drive Configuration 6 AT90S8515 0841G–09/01
AT90S8515 Architectural Overview The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed and the result is stored back in the register file – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S8515 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write-accessible in the I/O space. The 512-byte data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. 0841G–09/01 7
Page 1 and 2: Features • Utilizes the AVR ® RI
Page 3 and 4: AT90S8515 Description Block Diagram
Page 5: AT90S8515 current if the pull-up re
Page 9 and 10: AT90S8515 Figure 5. Memory Maps Pro
Page 11 and 12: AT90S8515 In the different addressi
Page 13 and 14: AT90S8515 two additional clock cycl
Page 15 and 16: AT90S8515 A 16-bit data address is
Page 17 and 18: AT90S8515 Indirect Program Addressi
Page 19 and 20: AT90S8515 I/O Memory The I/O space
Page 21 and 22: AT90S8515 into T by the BST instruc
Page 23 and 24: AT90S8515 $00f ldi r16,low(RAMEND)
Page 25 and 26: AT90S8515 External Reset An externa
Page 27 and 28: AT90S8515 • Bit 6 - INTF0: Extern
Page 29 and 30: AT90S8515 External Interrupts Inter
Page 31 and 32: AT90S8515 Sleep Modes Idle Mode Pow
Page 33 and 34: AT90S8515 Figure 29. Timer/Counter0
Page 35 and 36: AT90S8515 (TCCR1A and TCCR1B). The
Page 37 and 38: AT90S8515 Timer/Counter1 Control Re
Page 39 and 40: AT90S8515 Timer/Counter1 Output Com
Page 41 and 42: AT90S8515 Figure 32. Effects on Uns
Page 43 and 44: AT90S8515 1. In the same operation,
Page 45 and 46: AT90S8515 • Bit 2 - EEMWE: EEPROM
Page 47 and 48: AT90S8515 Serial Peripheral Interfa
Page 49 and 50: AT90S8515 pins are inputs. When SS
Page 51 and 52: AT90S8515 SPI Data Register - SPDR
Page 53 and 54: AT90S8515 If the 10(11)-bit Transmi
Page 55 and 56: AT90S8515 UART Control UART I/O Dat
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AT90S8515 BAUD Rate Generator The b
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AT90S8515 Analog Comparator The Ana
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AT90S8515 Default, the external SRA
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AT90S8515 I/O Ports Port A All AVR
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AT90S8515 Port B Port B is an 8-bit
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AT90S8515 • AIN0 - Port B, Bit 2
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AT90S8515 Figure 49. Port B Schemat
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AT90S8515 Port C Data Direction Reg
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AT90S8515 Port D Data Register - PO
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AT90S8515 Figure 54. Port D Schemat
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AT90S8515 Figure 58. Port D Schemat
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AT90S8515 the self-timed write oper
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AT90S8515 Chip Erase Programming th
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AT90S8515 Figure 62. Programming th
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AT90S8515 Parallel Programming Char
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AT90S8515 ing the third byte of the
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AT90S8515 Serial Programming Charac
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AT90S8515 Notes: 1. “Max” means
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AT90S8515 External Data Memory Timi
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AT90S8515 Typical Characteristics T
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AT90S8515 Figure 72. Idle Supply Cu
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AT90S8515 Analog Comparator offset
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AT90S8515 Sink and source capabilit
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AT90S8515 Figure 84. I/O Pin Source
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AT90S8515 Register Summary Address
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AT90S8515 Instruction Set Summary (
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AT90S8515 Packaging Information 44A
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AT90S8515 40P6 40-lead, Plastic Dua
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At90s8515 - Atmel Corporation

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