moving from system to circuit level in the design of digitial signal ...

OUTLINE 

MOVING FROM SYSTEM TO CIRCUIT LEVEL 

IN THE DESIGN OF DIGITIAL SIGNAL 

PROCESSING ALGORITHMS 

Sabih H. Gerez 

University of Twente & Bibix 

• Problem statement 

• Top-down design 

• Models of computation 

• Data flow 

• Register-transfer level (RTL) 

• C-based hardware design 

• Text-based and graphical design entry 

• Domain-specific design languages 

• Arx, a domain-specifid design language for RTL 

Bits & Chips Hardware Conference • June 9, 2011 • © Sabih H. Gerez 2 

PROBLEM STATEMENT 

COMPLEXITY: DIVIDE AND CONQUER 

• We need to build a digital signal processing (DSP) 

(sub)system. 

• The DSP algorithm is under development. 

• Fast system-level simulations are essential. 

• The DSP system will not be realized on programmable 

processors, but using dedicated hardware in an FPGA or 

ASIC technology. 

• How should the design be tackled? 

• Goal is to optimize: 

• Design time; 

• Design quality. 

abstract 

Abstraction levels 

concrete 


Bits & Chips Hardware Conference • June 9, 2011 • © Sabih H. Gerez 4

MODELS OF COMPUTATION 

• Each abstraction level has a corresponding model of 

computation (MoC). 

• Examples of often encountered MoCs: 

• Synchronous data flow (SDF) for DSP algorithms. 

• Register transfers for synchronous logic. 

• Differential equations for currents and voltages in circuits. 

SYNCHRONOUS DATA FLOW 

• Tokens carry data along edges of a graph. 

• Nodes perform computations and have fixed consumption 

and production rates. 

• “Untimed”, i.e. no direct relation to system clock in 

implementation. 

• Suitable for the specification of multi-rate DSP algorithms. 

3 

3 

2 

2 

4 

4 

Lee, E.A. and D.G. Messerschmitt, ”Synchronous Data Flow”, 

Proceedings of the IEEE, Vol. 75(9), pp 1235–1245, (September 1987). 



DATA-FLOW GRAPH EXAMPLE 

REGISTER-TRANSFER LEVEL DESIGN 

T 0 T 0 

T 0 

= delay element 

= FIFO with length 1 

• Characterized by state 

updates only on clock edge. 

• Descriptions are called clockcycle 

true. 

• Often coded in VHDL (or 

Verilog). 

• Specification of RTL in VHDL 

requires identification of 

language subset and coding 

style. 

• VHDL slow to simulate (eventdriven 

model). 

Primary 

inputs 

registers 

Comb. 

logic 

Primary 

outputs 

Second-order IIR filter 



IMPLEMENTATION IN TOOLS: TEXT OR GRAPHICS? 

GENERIC VS. DOMAIN-SPECIFIC LANGUAGES 

T 0 

• Consider SDF: 

• It is possible to use a general language as C for coding in 

• Tool based on graphical design entry is e.g. Synopsys System Studio. 

“data flow style” or “register-transfer style. 

• Example of domain-specific language for data flow is Silage: 

• Example of RTL in C: 

• Voluntarily stick to single-assignment code. 

y = b0*x + z2@1 

• Use static variables for registers and read these values before writing 

z2 = a1*y + b1*x + z1@1 

them. 

T_out sec(T_in x) { 

T 0 

z1 = a2*y + b2*x 

static T_reg z1 = 0; static T_reg z2 = 0; ... 

y = b0*x + z2; 

z2_nxt = a1*y + b1*x + z1; z1_nxt = a2*y + b2*x; 

z2 = z2_nxt; z1 = z1_nxt; // register update 

return(y); 

Hilfinger, P.N., "A High-Level Language and Silicon Compiler for Digital Signal 

Processing", Custom Integrated Circuit Conference, pp. 213-216, (1985). 

} 



PRACTICE IN SYSTEM-LEVEL-TO-RTL TRANSITION 

C-BASED HARDWARE DESIGN 

System 

Level 

RT Level 

abstract 

concrete 

System models 

often described in 

C or Matlab 

Costly manual 

translation 

(months) 

Hardware models 

in VHDL 

• Arguments in favor of C-based design: 

• Everybody knows C; we don’t want to teach new languages. 

• Lots of legacy C code. 

• High execution speed. 

• Many commerical products based on translation from 

C/C++/SystemC including: 

• Catapult (Mentor Graphics) 

• C-to-Silicon (Cadence) 

• Cynthesizer (Forte Design Systems) 

• Synphony C Compiler (Synopsys, formerly Synfora PICO) 

• AutoPilot (Xilinx, formerly AutoESL) 

• CyberWorkBench (NEC System Technologies) 



DISADVANTAGES OF C-BASED DESIGN 

• Arguments against C-based design: 

• Hardware design requires a different style of thinking than software 

design. 

• It takes time to learn the hardware-style of thinking, far longer than it 

takes to learn a new language. 

• It is an illusion to think that software engineers will become good 

hardware engineers by the availability of a C-to-HDL converter. 

• C was never invented with hardware in mind: 

• C cannot express parallelism. 

• Many language constructs do not make sense in hardware. 

• One needs to stick to a specific language subset and coding style. 

Edwards, S.A., The Challenges of Synthesizing Hardware from C-Like 

Languages, IEEE Design and Test of Computers, pp. 375-385, 

(September/October 2006). 


GRAPHICAL DESIGN ENTRY 

• Many solutions based on dedicated blocksets to be used in 

Simulink: 

• Mathwork’s own FPGA flow 

• Synphony Model Compiler (Synopsys) 

• Xilinx System Generator for DSP 

• Altera DSP Builder 

• Graphical design entry can be cumbersome compared to 

text-based entry: 

• One does not always want to instantiate an adder for every addition, a 

multiplexer for every if-statement, etc. 


DOMAIN-SPECIFIC DESIGN LANGUAGES 

ARX: A DOMAIN-SPECIFIC RTL LANGUAGE 

• All language constructs make sense in domain: 

• Entire language is synthesizable. 

• Designer does not need to bother about allowed subsets. 

• Straightforward language constructions: 

• Improve designer efficiency. 

• Lead to elegant designs. 

• Examples: 

• Bluespec 

• GEZEL 

Domain-specific 

RTL language: 

Arx 

Functional 

Bit-true 

Bit-true and 

clock-cycle-true 

• One language (Arx) for multiple 

levels. 

• Developed at University of Twente. 

• Arx eliminates manual translation 

from C to VHDL! 

• Correct by construction. 

C++ 

generator 

VHDL 

generator 

Verification 

with C-based 

simulation 

RTL synthesis 



ARX DOMAIN 

ARX EXAMPLE 

• Design of ICs or FPGAs for signal processing as e.g. found 

in: 

• Telecom 

• Image processing 

• Multimedia 

• Defense 

• Space, astronomy 

Clock and reset are 

implicit. 

sum 

r 

• Key is to descend to RTL from system-level design and 

necessity for fast cycle-true and bit-true simulations: 

• C++ code generated by Arx is based on zero-delay simulation. 

• Event-driven simulation (with factor 100 overhead!) does not make 

sense when almost all signals change in every clock cycle. 

data_in 

clear 

data_out 



LANGAUGE FEATURES 

• Explicit distinction between wires and registers. 

• Implicit clock and reset. 

• Generic data types allowing propagation of data types down 

hierarchy (e.g. floating-point to fixed-point refinement). 

• Data types for DSP, especially fixed-point data types. 

• Support for overflow and quantization modes. 

• Efficient simulation of fixed-point data types. 

• Simple: can be learned in one day! 

ABOUT BIBIX 

• University of Twente (UT) spin-off 

• Supported by the UT Centre for Telematics and Information 

Technology (CTIT). 

• Received an STW Valorisation Grant Phase 1 for feasibility 

study and market research on Arx. 

• Received with HDL Works a Point-One Feasibility Project for 

research on the application of Arx to FPGA design. 



ON-LINE FEATURES 

• Please visit: 

www.bibix.nl 

• The website gives access to: 

• On-line manual, 

• Web-based demonstration (upload Arx, download corresponding C++ 

and VHDL), 

• Questionnaire. 

• Feedback on Arx, requests for cooperation, very welcome. 

• Possibilities for free pilot designs. 


SUMMARY 

• Issues in moving from system level to RTL: 

• What MoC should be used when? 

• Generic or domain-specific implementation language? 

• Textual or graphical design entry? 

• A domain-specific language for the RTL MoC, e.g. Arx, 

bridges wall when descending from the system level. 

• Arx brings about that one source code generates: 

• C++-based simulation model optimized for simulation speed 

• VHDL code for synthesis. 

• The Arx approach: 

• Saves manual recoding time! 

• Is correct by construction!

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