tbp testengineering - Hardware Conference

tbp test engineering
Jan Lempers – Customer Project Manager
18-6-2012

product creation
Review
Customer
needs
Design
input
Design
process
Design
output
Engineering
sample
Prototype
Product
Verification
Pre-Qualification
Qulaification
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design for eXcellence (DfX)
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design for test
The aspects of the product design process whose goal is
to ensure that the testability of the end product is
competently and sufficiently developed.
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the ideal world
Pass
First-Pass
Yield
100%
Good
Faulty
Known Good
Boards:
100%
Slip: 0%
Production
Yield
100%
Test
Efficiency
100%
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est-in-class reality
no structural test,
only AOI.
Pass
First-Pass
Yield
93,77%
Good
Faulty
Known Good
Boards:
92,12%
Slip: 1,65%
Production
Yield
92,59%
Testway
Test
Efficiency
77,75%
Fall-Off
Rate:
6,22%
False
Rejects:
0,46%
Known Bad
Boards:
5,76%
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test strategy
how to get the proper test strategy
early involvement in design process
dialogue with developers during design
implement appropriate test strategy in the design
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test methods (a)
inspection systems
X-ray
automatic optical inspection (AOI)
structural test systems
boundary scan (BSC)
in-circuit (ICT)
flying probe (FP)
complementary test systems
functional test (FT)
system test
burn-in
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x-ray
what can be inspected:
• solder joints (BGA, QFN, …)
• shorts, opens (no cracks)
• discover fake components
pro’s and con’s:
quick program generation ( library )
no tool cost
exact diagnosis: ~ no troubleshoot time
no electrical test
depends on photo-interpretation of operator
development time:
• few minutes/part
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automatic optical inspection
what can be inspected:
• precense of components
• polarity of components
• optional solder joints
pro’s and con’s:
quick program generation ( library )
no tool cost
exact diagnosis: ~ no troubleshoot time
no electrical test
high false call rate (mainly solder)
development time:
• approximately 2 days (strongly dependent on library)
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oundary scan (1)
what can be tested:
• interconnects and BSC supported circuits
• opens/shorts between BSC nets
• can be used for programming purposes
pro’s and con’s:
quick program generation (if BSDL-files are provided)
test point saving
good diagnosis: ~ fast troubleshooting
programming (cpld, fpga)
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oundary scan (2)
pro’s and con’s:
coverage is limited to BSC-components
all command pins should be controllable
not all pins of a BSC-component are foreseen
with BSC-cells (e.g. clock inputs)
rather slow when BSC is used for advanced testing or
programming
development time:
• approximately 3,5 days (if BSDL-files are provided)
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in circuit test (1)
what can be inspected:
• resistors, capacitors, diodes, transistors,… (analog)
• shorts between all nets
• digital tests on component level
• testjet for non-functional ICs
• ISP (CPLD) device programming
pro’s and con’s:
fast test, simultaneous access to all nets
good diagnosis: ~ fast troubleshooting
boundary scan integration possible
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in circuit test (2)
pro’s and con’s:
fixture has to be developed
not flexible for changes
expensive equipment and tooling
development time:
• approximately 6 weeks
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flying probe test (1)
what can be tested:
unpowered board:
• resistors, capacitors, diodes, … (analog)
• transistors, FETs, zenerdiodes (digital)
• shorts between nets with short risk
• diode to ground on digital components
powered board:
• voltages (current limitation), currents
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flying probe test (2)
pro’s and con’s:
quick program development from CAD data
flexible for small changes
fixture replaced by flying probes => no fixture development
good diagnosis: ~ fast troubleshooting
open/short checker
boundary scan integration possible
long run time only for prototyping and low volume
limited coverage (MDA)
development time:
• approximately 1 day
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test methods (b)
BSC
X-ray
ICT
FT
AOI
FPT
combination
test
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determine the test strategy
Schematic
BSDL file
TestWay
DfT report,
TestPoint Saving,
Test Strategy
CAD file
(ODB++,
GenCad, …)
TestExpert
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dft analysis - our approach
our goal
• maximize manufacturing test coverage and efficiency
result contains:
• access result for test process and related coverage
indicating blocking issues
• proposal to improve the
coverage, according to the
process
• design guideline where
additional access is required
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the benefit of dft analysis
test coverage report WITHOUT
preliminary DfT analysis
(AOI + ICT + BSC)
test coverage report WITH
preliminary DfT analysis
(AOI + ICT + BSC)
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Cost
structural vs functional test
Troubleshoot (min)
Development (h)
Run-time (10s)
AOI FPT ICT BSC FT
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slip-through vs test strategy
test strategy: AOI, FP, BS >
< test strategy: AOI, ICT, BS
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cost efficiency
cost per board
# PCBAs
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equirements for dft
early involvement
edif file (dft analysis on schematic)
detailed CAD data (ODB++ preferred)
bill of materials
searchable schematics (pdf)
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test strategy - summary
agreed slip
take test coverage into account at design
reduce product cost (troubleshoot, low skill operators)
reduce custom test investments
controllable delivery performance
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thanks for your attention
questions
jlempers@tbp.nl
www.tbp.eu
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