1275_Premkumar.ppt [Read-Only]

Accelerating Chip-level Routing
and Design
Johnny Premkumar
National Semiconductor
Corporation
1

Accelerating Chip-level Routing and
Design
• Background/Motivation
• Routing Preparation
• Chip Level Routing and Optimization
• Flow Diagram
• Conclusion/Recommendations
2
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Background
– Majority of analog/mixed-signal chip assembly is done
manually.
– There is a lack of a structured chip-level design flow.
– Drawbacks – time consuming, expensive.
– Difficult to reuse previous designs.
– High risk of errors being introduced.
– Poor yield, reliability.
– The number of analog constraints may be too many
for a human designer to keep up.
3
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Motivation
– Complexity of circuit designs keep increasing.
Analog/Mixed signal portions are most difficult.
– First-pass silicon success is critical to save money and
time.
– Reduce human error and enhance proper chip
functionality.
– Maximize design productivity.
– Produce optimal layouts.
– Shorter time to market.
4
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Device Level Place and Route
– Advanced pcells developed for analog cells.
– Neocell - a analog device level place and route tool
from Cadence. Process based technology files
developed.
– Virtuoso Custom Placer(VCP) – a row based
placement tool. Placement of digital blocks/ standard
cells.
– Virtuoso Custom Router (VCR) – a device level
automatic router.
5
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Routing Preparation
– CCT rules.
– Generate abstract Views.
– Top-level layout generation and placement.
– Pre-routes
• Power/Ground rails
• Wires/Segments with multiple contacts/vias
• Complicated matched/symmetry routing
• Critical nets
6
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Routing Specification
– CCAR – Advanced chip-level router for analog designs
and small digital designs.
• Layout is automatically DRC and LVS clean.
– Cadence Chip Assembly Router(CCAR) do file setup :
• Initialization
• Rules
• Global Route
• Detail Route
• Post Route clean up
– Export layout in abstract format from layout
environment to CCAR.
7
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Top-level Routing
– Execute CCAR do file for automatic routing.
• Global Route, Congestion Analysis
– Interactive Routing for tweaking layout and fixing
errors.
– Run detail route.
– Examine results.
– Run more detail route if necessary to improve routing
results.
8
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Top-level Routing (Cont’d)
– Improve the route completion and number of
unconnects – space out instances/blocks, interactive
routes/edits.
– Re-run detail route.
– Import layout into the Layout tool(VXL) and run
physical verification. If needed re-export design to
CCAR.
• Post Route
– Import final design into VXL.
– Physical Verification: DRC, LVS.
9
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• CCAR
10
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
Flow/Methodology
Digital Cells(VXL,
Pcells, VCP, VCR )
Device Level Layout
Design (ACPD flow)
Analog Cells(Neocell,
Pcells)
Pre-routes (Wire
Editor)
Top Level Placement
(VXL)
Abstract Views (Abstract
Generator)
CCAR do
files
CCT rules
Top Level Automatic Routing (CCAR)
Load CCAR do file
Global Route(Analyze)
Detail Route
Fix Conflicts, Interactive Routes
ECO, Post Route
VXL, Physical Verification
11
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Future enhancements
– Integrated Floor Planner for mixed-signal designs to
enable top-down design.
– An advanced compaction tool.
– Increased flexibility for interactive edits in CCAR.
– Layout Editing capabilities within CCAR to limit
import/export time.
12
© 2004 National Semiconductor Corporation

Accelerating Chip-level Routing and
Design
• Conclusion
– Interations are greatly reduced. Reduces the
chances for error.
– Design re-use can be utilized.
– ECO changes in the circuit can be incorporated into
the layout easily.
– A good percentage of automation.
– Layout design cycle time is shortened. Saves time to
market.
– More time spent on optimization. Results in better
yield. Ultimately the final layout can be improved.
13
© 2004 National Semiconductor Corporation