Tutorial: Introduction to CUDA Fortran | GTC 2013

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GPU Accuracy • FERMI GPUs are IEEE-754 compliant, both for single and double precision • Support for Fused Multiply-Add instruction (IEEE 754-2008) • Results with FMA could be different* from results without FMA • In CUDA Fortran is possible to toggle FMA on/off with a compiler switch: -Mcuda=nofma • Extremely useful to compare results to “golden” CPU output • FMA is being supported in future CPUs Compute pi in single precision (seed=1234567 FMA disabled) Samples= 10000 Pi=3.16720009 Error= 0.2561E-01 Samples= 100000 Pi=3.13919997 Error= 0.2393E-02 Samples= 1000000 Pi=3.14109206 Error= 0.5007E-03 Samples= 10000000 Pi=3.14106607 Error= 0.5267E-03 Samples= 100000000 Pi=3.14139462 Error= 0.1981E-03 *GPU results with FMA are identical to CPU if operations are done in double precision
Reductions on GPU 3 1 7 0 4 1 6 3 • Parallelism across blocks • Parallelism within a block • No global synchronization 4 7 5 9 11 14 – two-stage approach (two kernel lauches), same code for both stages 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 Level 0: 8 blocks 3 1 7 0 4 1 6 3 4 7 5 9 11 14 25 Level 1: 1 block
Page 1 and 2:
Introduction to CUDA Fortran
Page 3 and 4:
Introduction • CUDA is a scalable
Page 5 and 6:
Heterogeneous Programming • Host
Page 7 and 8:
Data Transfers program copyData use
Page 9 and 10:
Data Transfers program copyData use
Page 11 and 12:
F90 Array Increment module simpleOp
Page 13 and 14:
CUDA Fortran - Device Code F90 modu
Page 15 and 16:
Execution Model Software Thread Thr
Page 17 and 18:
Mapping Arrays to Thread Blocks •
Page 19 and 20:
Built-in Variables for Device Code
Page 21 and 22:
Multidimensional Example - Host •
Page 23 and 24:
2D Example - Device Code module sim
Page 25 and 26: Kernel Loop Directives (CUF Kernels
Page 27 and 28: Reduction using CUF Kernels • Com
Page 29 and 30: Compilation • pgfortran - PGI’s
Page 31 and 32: Separate Compilation module kernel_
Page 33 and 34: Host-Device Transfers • Host-devi
Page 35 and 36: Page-Locked Data Transfers • Page
Page 37 and 38: Asynchronous Data Transfers • Asy
Page 39 and 40: GPU/CPU Synchronization • cudaDev
Page 41 and 42: Outline • Introduction • Perfor
Page 43 and 44: Misaligned Data Access • Use arra
Page 45 and 46: Strided Data Access • Use array i
Page 47 and 48: Shared Memory • On-chip • All t
Page 49 and 50: Matrix Transpose - Shared Memory at
Page 51 and 52: Textures • Different pathway for
Page 53 and 54: Textures - Host Code program tex us
Page 55 and 56: Execution Configuration • GPUs ar
Page 57 and 58: Thread-Level Parallelism attributes
Page 59 and 60: Thread-Level Parallelism • Mimic
Page 61 and 62: Instruction-Level Parallelism No Sh
Page 63 and 64: Calling CUBLAS from CUDA Fortran
Page 65 and 66: Calling Thrust from CUDA Fortran C
Page 67 and 68: CUDA Fortran Sorting with Thrust pr
Page 69 and 70: Convolution Example A B Perform con
Page 71 and 72: program driver use cudafor use cuff
Page 73 and 74: CUDA Libraries from CUDA Fortran
Page 75: Computing π pgf90 -O3 -Mpreprocess
Page 79 and 80: Computing π with CUDA Fortran Kern
Page 81 and 82: Computing π with an Atomic Lock In
Page 83 and 84: Multi-GPU Programming • Multi-GPU
Page 85 and 86: Multi-GPU Memory Allocation • All
Page 87 and 88: Unified Virtual Addressing • CPU
Page 89 and 90: Direct Transfers • Once direct ac
Page 91 and 92: Direct Transfer Example - Device Co
Page 93 and 94: Direct Transfer Example - Host Code
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Tutorial: Introduction to CUDA Fortran | GTC 2013

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