Tutorial: Introduction to CUDA Fortran | GTC 2013

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Computing π with CUDA Fortran Kernels attributes(global) subroutine final_sum(partial,nthreads,total) integer, intent(in) :: partial(nthreads) integer, intent(out) :: total integer, shared :: psum(*) integer :: index, inext index=threadIdx%x ! load partial sums in shared memory psum(index)=partial(index) call syncthreads() inext=blockDim%x/2 do while ( inext >=1 ) if (index
Computing π with an Atomic Lock Instead of storing back the partial sum: ! Each block writes back its partial sum if (index == 1) partial(BlockIdx%x)=psum(1) use an atomic lock to ensure that one block at the time updates the final sum: if (index == 1) then do while ( atomiccas(lock,0,1) == 1) !set lock end do partial(1)=partial(1)+psum(1) ! atomic update of partial(1) call threadfence() ! Wait for memory transaction to be visible to all the other threads lock =0 ! release lock end if partial(1)=0 call sum(deviceData,partial,N) inside=partial(1)
Page 1 and 2:
Introduction to CUDA Fortran
Page 3 and 4:
Introduction • CUDA is a scalable
Page 5 and 6:
Heterogeneous Programming • Host
Page 7 and 8:
Data Transfers program copyData use
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Data Transfers program copyData use
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F90 Array Increment module simpleOp
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CUDA Fortran - Device Code F90 modu
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Execution Model Software Thread Thr
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Mapping Arrays to Thread Blocks •
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Built-in Variables for Device Code
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Multidimensional Example - Host •
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2D Example - Device Code module sim
Page 25 and 26:
Kernel Loop Directives (CUF Kernels
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Reduction using CUF Kernels • Com
Page 29 and 30: Compilation • pgfortran - PGI’s
Page 31 and 32: Separate Compilation module kernel_
Page 33 and 34: Host-Device Transfers • Host-devi
Page 35 and 36: Page-Locked Data Transfers • Page
Page 37 and 38: Asynchronous Data Transfers • Asy
Page 39 and 40: GPU/CPU Synchronization • cudaDev
Page 41 and 42: Outline • Introduction • Perfor
Page 43 and 44: Misaligned Data Access • Use arra
Page 45 and 46: Strided Data Access • Use array i
Page 47 and 48: Shared Memory • On-chip • All t
Page 49 and 50: Matrix Transpose - Shared Memory at
Page 51 and 52: Textures • Different pathway for
Page 53 and 54: Textures - Host Code program tex us
Page 55 and 56: Execution Configuration • GPUs ar
Page 57 and 58: Thread-Level Parallelism attributes
Page 59 and 60: Thread-Level Parallelism • Mimic
Page 61 and 62: Instruction-Level Parallelism No Sh
Page 63 and 64: Calling CUBLAS from CUDA Fortran
Page 65 and 66: Calling Thrust from CUDA Fortran C
Page 67 and 68: CUDA Fortran Sorting with Thrust pr
Page 69 and 70: Convolution Example A B Perform con
Page 71 and 72: program driver use cudafor use cuff
Page 73 and 74: CUDA Libraries from CUDA Fortran
Page 75 and 76: Computing π pgf90 -O3 -Mpreprocess
Page 77 and 78: Reductions on GPU 3 1 7 0 4 1 6 3
Page 79: Computing π with CUDA Fortran Kern
Page 83 and 84: Multi-GPU Programming • Multi-GPU
Page 85 and 86: Multi-GPU Memory Allocation • All
Page 87 and 88: Unified Virtual Addressing • CPU
Page 89 and 90: Direct Transfers • Once direct ac
Page 91 and 92: Direct Transfer Example - Device Co
Page 93 and 94: Direct Transfer Example - Host Code
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Tutorial: Introduction to CUDA Fortran | GTC 2013

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