Synchronous Serial IO Serial Peripheral Interface (SPI) Multi ...

Synchronous Serial IO
• Send a separate clock line with data
– SPI (serial peripheral interface) protocol
–I 2 C (or I2C) protocol
• Encode a clock with data so that clock be
extracted or data has guaranteed transition density
with receiver clock via Phase-Locked-Loop (PLL)
– IEEE Firewire (clock encoded in data)
– USB (data has guaranteed transition density)
Serial Peripheral Interface (SPI)
Three wire interface: SCK (clock), SDO (serial data out),
SDI (Serial Data Out)
SDO, SDI is uni-directional, but communication can occur in
both directions at same time (full-duplex).
From: The Quintessential PIC Microcontroller, Sid Katzen
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Multi-Receiver
Each peripheral must have a SELECT line that
is asserted that indicates this serial
communication is for them.
I 2 C (Inter-Integrated-Circuit) Bus
I2C is a two wire serial interface.
16F873
Vdd
10K
Microchip 24LC515
SCL
SCL A2
Vdd
SDA
10K
SDA
A1
A0
SCL – clock line
SDA – data
(bidirectional)
SCL
SDA
A2
A1
A0
From: The Quintessential PIC Microcontroller, Sid Katzen V 0.1 3
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I 2 C Features
• Multiple receivers do not require separate select
lines as in SPI
– At start of each I 2 C transaction a 7-bit device address is
sent
– Each device listens – if device address matches internal
address, then device responds
• SDA (data line) is bidirectional, communication is
half duplex
• SDA, SCLK are open-drain, require external
pullups
– Allows multiple bus masters (will discuss this more
later).
Example: I 2 C Serial EEPROM
Will use the Microchip 24LC515 Serial EEPROM to discuss I 2 C
operation.
The 24LC515 is a 64K x 8 memory. This would require 16
address lines, and 8 data lines if a parallel interface was
used, which would exceed the number of available IO pins
our PIC16873!!!
Putting a serial interface on a memory device lowers the
required pin count.
Reduces speed since data has to be sent serially, but now
possible to add significant external storage to a low pincount
micro controller.
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I 2 C Device Addressing
Each I2C device has either a 7-bit or 10-bit device address.
We will use an I2C EEPROM and an I2C DAC (Digital-to-
Analog Converter, MAX517) in lab. Both of these devices
have a 7-bit address.
Upper four bits are assigned by device manufacturer and are
hardcoded in the device. Lower three bits are used in
different ways by manufacturer.
Microchip 24LC515 LC515 control byte (contains slave address):
SCL A2
7 6 5 4 3 2 1 0 R/W = 1
for read, 0
A1
1 0 1 0 B0 A1 A0 R/W for write.
SDA A0 ‘B0’ is block select (upper/lower 32K). A1, A0
are chip selects, four devices on one bus.
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IDLE: SCL,
SDA high.
START: high
to low
transition on
SDA while
SCL high.
Valid data:
While clock is
high, data
valid and
stable.
I2C Transmission
Data
changes
while
clock is
low.
STOP: low to
high transition
on SDA while
SCL high.
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Acknowledgement
ACK sent by slave after every 8-bits received. Master releases line
(stops driving), samples line on next clock.
Slave MUST pull line low. If Master does not detect ACK, then
sets error bit. If Slave does not pull line low, the pullup resistors
will pull the line low.
Most common cause of ACK error – incorrect device address.
Byte Write Operation
• Byte Write: used to write one byte
– Send Control Byte, High address byte, low address
byte, data.
– After data is sent, takes 5 ms for write to complete
– SLOOOOOWWWWWW....
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‘0’ indicates write mode.
‘X’ because block select bit
chooses high or low 32K.
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Page Write Operation
• Send a block of 64 bytes, then perform write
– Send starting address, followed by 64 bytes
– After 64 bytes sent, wait 5 ms for write to complete
– Much faster than individual writes
Address must be on a page boundary. For page size = 64 = 0x40,
starting address must be a multiple of 64.
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Speed Comparison
• Assume a 400 Khz I 2 C bus, 2.5 us clock period
(2.5 e-6)
• Random write:
– 9 bit transmission = 2.5 us * 9 = 22.5 us
– 5 ms + 22.5 us* 4 (control,addhi,addlo,data) =5.09 ms
– For 64 bytes = 325 ms approximately, not counting software
overhead.
• Page Write
– 67 bytes total (control, addhi, addlo, data)
– 5 ms + 67 * 22.5 us = 6.5 ms!!!
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Checking for end-ofwrite
Timing on write is
guaranteed to finish after 5
ms. But can end sooner; to
determine if write finished
use polling method.
No ACK means device is
still busy with last write.
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Read Operation: Current Address
• An internal counter is used to keep track of last
address used
• A current address read uses this address, only
sends the command byte
– Internal counter incremented after read operation
‘1’ indicates read
operation
‘no ack’ because slave is
driving data back to
master.
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Random Read Operation
• Must first set the internal address counter by
starting a write operation, but aborting by not
sending data byte
Sequential Read
• Like a current address read, but after Slave sends
data byte, Master sends ACK instead of STOP
– Slave then sends next byte
– Can do this from 0x0000h to 0x7FFF (lower 32K block). When
0x7FFF is reached, address rolls over to 0x0000
– Upper block goes from 0x8000 to 0xFFFF; at 0xFFFF address
rolls over to 0x8000
– Internal address counter is only 15 bits wide.
Aborted random write (address only,
no data)
Current address read
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PIC 16 I 2 C Registers
• Synchronous Serial Port on PIC implements I2C
• Registers are:
– SSPCON – control register - we will always set this to
0x28 which enables I2C MASTER mode.
– SSPCON1 – control register - used to initiate a
START/STOP conditions, indicates if ACK has been
received
– SSPSTAT – status register – check this to see if byte
finished transmitting, or byte has been received
– SSPBUF – read/write to this register for data transfer
– SSPADD – used to control clock rate
I 2 C on the PIC16
• Will always use master mode on the PIC16
– This means that the PIC will always initiate all I 2 C bus
activity
• To set I2C clock rate, write 8-bit value to the
SPADD register
– Clock rate = Fosc/(4 *(SSPADD+1))
• I 2 C standard defines 100 KHz and 400 KHz but in
reality just about any clock rate from DC to 400
KHz wors
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Lab #8: Read/Write to Serial EEPROM
• Lab #8 has you read/write to a Serial EEPROM
via the I2C bus
• The files i2cmsu.h, i2cmsu.c define interface
subroutines for the I2C bus
– This file also has subroutines for random read/write,
block read/write for the serial eeprom
• The file memblk.c tests uses the subroutines to
read/write data to the serial EEPROM.
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i2cmsu.c Subroutines
• i2c_idle() – wait for idle condition on I2C bus
• i2c_Start() – send a START and wait for START
end
• i2c_Stop() – send a STOP and wait for STOP end
• i2c_doAck() – do an ACK cycle
• i2c_doNak() – do a NACK cycle
• i2c_WriteTo(address) – do a i2c_Start(), then send
address to I2C bus.
• i2c_PutByte(byte) – write byte to I2C, wait for
finish, then get an ACK
• i2c_GetByte() – get a byte from I2C bus
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Random Read: memread(cmd,addr)
i2c_Writeto (write_cmd)
i2c_PutByte (address_hibyte)
i2c_PutByte (address_lobyte)
i2c_Stop()
i2c_Writeto (read_cmd)
i2c_GetByte ()
i2c_Stop()
cmd is unsigned char
that has EEprom i2c
device address
addr is unsigned char is
memory address within
EEprom
Set internal address
counter.
Read byte from
current address
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memread(cmd,addr)
Does a random read of EEPROM
/* random read */
unsigned char mem_read(unsigned char cmd,int addr) {
unsigned char hbyte, lbyte, val;
if (addr & 0x8000) { // if MSB set , set block select bit
cmd = cmd | 0x08;
}
hbyte = (addr >> 8) & 0x7F; // high address byte
lbyte = (addr) & 0xFF; // low address byte
i2c_WriteTo(cmd); // send write cmd, do this to set address counter
i2c_PutByte(hbyte); // send high address byte
i2c_PutByte(lbyte); // send low address byte
i2c_Stop();
// send stop
cmd = cmd | 0x1; // set read bit
i2c_WriteTo(cmd); // send read cmd, address set by previous cmd
val = i2c_GetByte(); // read data
i2c_Stop();
// send stop
return(val);
}
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i2c_Writeto (write_cmd)
i2c_PutByte (address_hibyte)
i2c_PutByte (address_lobyte)
i = 0;
i2c_PutByte (); i++
i = 64?
i2c_Stop()
Page Write
set starting
address.
Send 64 bytes.
Page (Block) Write
/* block write */
void block_mem_write(unsigned char cmd,int addr, char *buf) {
unsigned char hbyte, lbyte, val;
hbyte = (addr >> 8) & 0x7F; // high address byte
lbyte = (addr) & 0xFF; // low address byte
i2c_WriteTo(cmd); // send write cmd
i2c_PutByte(hbyte); // send high address byte
i2c_PutByte(lbyte); // send low address byte
for (k=0;k

i2c_Writeto (write_cmd)
i2c_PutByte (address_hibyte)
i2c_PutByte (address_lobyte)
i2c_Stop()
i2c_Writeto (read_cmd)
i2c_GetByte (); i++
i = 64?
yes
i2c_Stop()
no
i2c_doAck();
Block Read
set starting
address.
Send read
command
Use sequential
read to get 64
bytes.
Sequential read can read up
to 32K, block size of 64
bytes was arbitrary
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Block Read in C
/* block read */
void block_mem_read(unsigned char cmd,int addr,char *buf) {
unsigned char hbyte;
unsigned char lbyte;
unsigned char k;
if (addr & 0x8000) {
// if MSB set , set block select bit
cmd = cmd | 0x08;
}
hbyte = (addr >> 8) & 0x7F; // high address byte
lbyte = (addr) & 0xFF; // low address byte
i2c_WriteTo(cmd); // send write cmd, do this to set address counter
i2c_PutByte(hbyte); // send high address byte
i2c_PutByte(lbyte); // send low address byte
i2c_Stop();
// send stop
cmd = cmd | 0x1; // set read bit
i2c_WriteTo(cmd);
for (k=0;k

i2c_PutByte()
i2c_PutByte(unsigned char byte) {
i2c_idle();
/* write data */
SSPBUF = byte;
/* wait until finished */
while(bittst(SSPSTAT,2));
/* wait for acknowledge */
while(bittst(SSPCON2,6));
}
i2c_FastPutByte deletes this call.
SSPBUF holds
outgoing data
Cleared when
transmit finished.
Cleared when
ACK received.
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i2c_WriteTo
i2c_WriteTo(unsigned char addr) {
/* first, send start */
i2c_Start();
SSPBUF = addr; /* write data */
/* wait until finished */
while(bittst(SSPSTAT,2));
/* wait for acknowledge */
while(bittst(SSPCON2,6));
}
SSPBUF holds
outgoing data
Cleared when
transmit finished.
Cleared when
ACK received.
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i2c_GetByte()
unsigned char i2c_GetByte() {
unsigned char byte;
i2c_idle();
/* initiate read event */
bitset(SSPCON2,3);
/* wait until finished */
while(bittst(SSPCON2,3));
while (!(bittst(SSPSTAT,0)));
byte = SSPBUF; /* read data */
return(byte);
Get data
}
Enable receive
Will be cleared when
finished.
Receive buffer
should be full
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Lab 9: I2C & Serial EEPROM
Goal: Capture streaming data from serial port, store to serial
EEPROM
Capture 64
bytes from
serial port to
buffer
Page Write of 64
bytes
Interrupt service routine
stores bytes in a buffer.
Problem: While writing
bytes to serial EEPROM,
more bytes are arriving!!!
Solution: Use two buffers! Second
buffer captures data while first
buffer data written to EEPROM.
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0
Save char in buff0
64 bytes?
yes
Write_flag = 1
Char arrival
triggers interrupt
Active buffer?
no
no
exit interrupt service
1
Two Buffers
Interrupt Service
Subroutine
Save char in buff1
64 bytes?
yes
Write_flag = 1
At least one of the 64 byte buffers
MUST be in bank1, not enough
room for both in bank0.
While writing data to
EEPROM from one
buffer, use other buffer
to receive incoming data.
ISR sets write_flag to
indicate to main() that 64
bytes has been received,
and that
block_mem_write()
should be called.
active_buffer flag set by
main() to indicate what
buffer the ISR uses for
byte storage.
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Streaming Write Loop: main()
Streaming Write Loop
0
Page write buff0
Write_flag?
Active buffer?
Active buffer = 1 Active buffer = 0
1
Write_flag = 0
addr = addr + 64
0
1
Page write buff1
Wait for interrupt service
routine to fill a buffer.
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What do you have know?
• Serial Peripheral Interface (SPI) – how is this
different from I2C?
• I2C Protocol
– What is start, stop, ack conditions, purpose of each
– How is data sent, received
– Device addressing
• Serial EEPROM
– Sequential, Random Read operations
– Random, Block Write operations
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