FPGA Anti-Copy Protection System - ALSE

June 2009 – v 1.7
Advanced Logic Synthesis for Electronics
www.ALSE-FR.com
Introduction to ALSE's
Anti-Copy Protection Kit
A.L.S.E.
166, Bvd du Montparnasse
75014 – PARIS
Tél. : +33 (0)1 42 79 51 38
http://www.alse-fr.com/english
© ALSE Introduction do ALSE's Anti-Copy Protection 1

I. INTRODUCTION
Inadequate design security is emerging as one of the single largest threats to the intellectualproperty-based
economies of the modern world. Consequences of inadequate design security can
include lost revenue due to counterfeit products and increased liability due to product tampering.
Copy protection issues do not concern ASIC designers, but most SRAM-based FPGA designers
must keep in mind that the precious bitstream can very easily be cloned and reused by
unauthorized parties. Some FPGA vendors offer now specific families that implement protection
schemes, but we'll see that any FPGA can benefit from the simple solution developed by ALSE.
ALSE's solutions
As a response to this copy protection challenge, ALSE introduced two highly cost-effective
fixed-secret authentication schemes based on a cheap and secure authentication device. In
both solutions, the authentication is achieved through a variable challenge-response mechanism
and user secret keys. Communication with the host is achieved through a single wire interface,
in order to avoid consuming precious I/Os, and to simplify the board layout.
The solution is based on :
1. A small footprint cryptography & verification engine inside the FPGA (~380 Logic Cells).
2. An external authentication component which embed is the same crypto engine.
One version of the Protection kit is based on Intersil components (ISL 6296 / ISL 9206), the
other version can be fitted in any secure and inexpensive CPLD, like Altera's MaxII
EPM240. For quantities, such a device should cost in the 1 € range.
3. A one-wire communication protocol allowing the FPGA to challenge the external device
with an interrogation code and retrieve the response to be compared with the value
calculated internally.
Thanks to the small FPGA area required, the one-wire communication, and the low cost and small
size of the authentication engine, adding security to just any FPGA design is both easy and
affordable, even if the decision to protect the design comes as an after-thought.
Due to these features, it is quite easy to add this anti-copy scheme even to a design that wasn't
planned initially to implement it. A small PCB area and one or two I/Os available on the FPGA are
sufficient to secure a design.
Important : any FPGA can be protected with our Anti-Copy Kit. The customer must specify, at time
of purchase, the unique device family to protect.
Any processor-based system could potentially be protected by our Anti-Copy Max II device, but
ALSE will not provide the internal algorithm, as would be necessary to implement the protection in
software. As a consequence, this Anti-Copy Kit is not usable for processor protection schemes,
except when the processor is embedded in an Altera FPGA (SOPC).
An advantage of the CPLD protection (as opposed to using a dedicated device) is that the CPLD
can be reprogrammed, thus providing the possibility to update or change the protection scheme at
any time on an existing board without any hardware change.
Commercial model
ALSE offers a single price for protecting a single but complete FPGA family for as many projects
as desired within the same company, using a unique set of encryption keys.
The generation of other sets for different FPGA families or different encryption keys is a (very
affordable) option.
Advantages
This Anti-Copy Protection Kit offers many advantages :
➢ Several authentication device are possible with no risk of obsolescence (CPLD).
➢ Since no source code is available, the risk of leaks within the company can be easily controlled.
Furthermore, there is no specific tool or development system to purchase.
© ALSE Introduction do ALSE's Anti-Copy Protection 2

➢ There is no development cost.
➢ Integration in the original design is very easy and can take place very late in the project.
➢ There is no cost (and no royalty) for producing or using as many authentication devices as
desired, and no minimal quantity of authentication devices to purchase.
➢ The protection scheme can potentially be upgraded or changed later.
II.
THEORY OF OPERATION
The ALSE Protection IP located inside the user device (SRam-based FPGA) generates a random
32 bits challenge code at randomized points in time.
This challenge code is used by the internal encryption engine which produces an 8 bits
authentication code, which is the expected response.
This challenge code is also transmitted over the single-wire link to the external authentication
device.
The external device is triggered, receives the 32 bits challenge code, and starts the exact same
computation as the FPGA, in parallel. At the end of calculation, the external device sends back its
result to the User device over the single-wire link.
The FPGA verifies some timing and receives the 8 bits response code.
If the timings, response code and the expected value do not match, it means the external device is
not present, a fake or that there was an error in the communication. For this reason, and for
increased protection, the checker does not immediately report a cloning situation. The internal
logic has some tolerance, and the cloning error will only appear after repeated mismatches.
In this case, the User design can then either cease to operate or operate with diminished
functionality, such as in a demo mode, or enter in a safety mode, etc...
Here is below the copy protection functional diagram.
User FPGA
User Board
User Specific
Design
ALSE's
Protection IP
Clock
Reset
XSDATA
Single Wire
Interface
Anti-Copy
Authentication
Device
(CPLD or ISL)
Authentication
Engine
© ALSE Introduction do ALSE's Anti-Copy Protection 3

III.
HARDWARE IMPLEMENTATION EXAMPLE USING A MAX II CPLD
The picture below shows a board designed many years ago where the protection has been added.
The protected FPGA (Cyclone 1C20) is visible in the middle-left.
The anti-copy CPLD (Max II) is on the upper right corner of the picture, and the EPCS device on
the lower left corner.
The board was created with a few extra links between the Max II and the Cyclone FPGA beyond
the two that are used (in case other functions would be desired).
The Max II uses a MAXCLK signal (provided by the Cyclone chip) as a clock input .
VI. OBTAINING THE ANTI-COPY KIT
Upon request, ALSE will send a commercial quotation or Proforma Invoice for the acquisition of an
Anti-Copy Kit.
Upon purchase, the customer provides the following information to ALSE :
– Whether CPLD or ISL solution is retained
– FPGA's internal system clock frequency.
– In case of CPLD : retained CPLD family and reference + selected pin numbers for XSDATA,
CLOCK (and optionnaly RESET).
As next step, ALSE generates a unique set of parameters and encryption engine configuration,
and creates the deliverables.
The customized deliverables are :
– Customer-specific Programming file for the selected CPLD (if not ISL).
– Encrypted Netlist file for the FPGA target selected by the customer.
– Quartus License feature to enable compilation of the encrypted netlist for Altera FPGAs.
– Other deliverable (like sample project etc).
© ALSE Introduction do ALSE's Anti-Copy Protection 4

Special case of ISL Authentication devices
When the protection scheme adopts one Intersil device, ALSE delivers a special block (to fit inside
the FPGA) for in-site programming of the ISL. The use of this block is optional sicne the ISL
devices can be programmed at time of purchase or by specific programmers, or with a board
tester, but this function offers the user the possibility to fully control the production of the
authentication device : the FPGA is temporarily loaded with the programmer, which runns for a few
seconds. It also allows to program a set of secret keys at the last moment.
In any case, the customer should be extremely careful to program the exact desired number of
anti-copy devices and make sure this prohgramming operation is confidential and secure !
The other step is to protect the FPGA by including the Protection IP's netlist file in the final
compilation, then remove this file and all compilation results except the final (protected) FPGA
bitstream, which can be left unprotected. This step when applied to Altera FPGAs requires a
specific license (feature), generated by ALSE along with the protected netlist file, to be added to
the Altera license. This feature allows Quartus II to compile the project included the protection
scheme and to generate the programming file(s). Generating simulation (debugging) files is not
allowed by the license in order to avoid weakening the protection. This increases the security.
For obvious safety reasons, ALSE does not offer to deliver either the CPLD or the FPGA anti-copy
verifier as source code !
SUMMARY
Protecting just any FPGA design is easy and cost-effective using ALSE's Anti-Copy Protection Kit.
This protection is not as secure as other monetary grade solutions, and may not resist major
tampering efforts but it is a good compromise and should be enough to discourage most
counterfeiting attempts for industrial solutions.
Remember : it's never too late (you don't need much PCB space and only one wire) !
Bert Cuzeau
CTO A.L.S.E.
Tel +33 1 4279 5138
© ALSE Introduction do ALSE's Anti-Copy Protection 5