DDR3,DDR2,Multi-port Memory Controller BA317 - Barco

DDR3,DDR2,Multi-port Memory Controller
Key Features
BA317
FactSheet
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● Supports SDR, DDR, DDR2 and DDR3 memory devices (discrete and dims)
● Multi-port controller;
● Highly configurable;
● Multi-port arbiter designed to achieve high bandwidth;
● Supports a wide variety of FPGA (Virtex-4, Virtex-5, Virtex-6, Spartan-3, Stratix-II, Stratix-III, Stratix-IV,
Cyclone-II, CycloneIII, Arria-II GX…);
User Interface
● Simple generic interface;
● Each port can be individually configured;
● FIFO included (configurable);
● Each port can have its own asynchronous clock;
● Each port can have a different data bus width;
● Can be connected to PLB/OPB bus on Xilinx
device (via IPIF interface).
Physical Interface
● DDR/DDR2/DDR3 PHY interface is included for
many FPGA;
● Number of address bits, number of chip select,
data width… are configurable;
● Automatically generates the initialization
sequence and periodic refresh;
● Optimized for burst of 8 data;
● SDRAM module serial presence supported.
BA317
SPD
interface
SPD
EEPROM
User port
User port
SDRAM
controller
core
Physical
interface
SDRAM
User port
Data bufferization
Data width translation
SDRAM burst generation
Clock domain crossing
Arbitration
SDRAM command generation
SDRAM initialization
SDRAM refresh control
Address mapping
Clock generation
Double Data Rate conversion
Read data resynchronization
Figure 1 - BA317 Block Diagram
Doc.Version: 1.5
www.barco-silex.com

General description
The BA317 is a highly configurable DDR/DDR2/DDR3-SDRAM Memory Controller developed, validated &
licensed by BARCO-Silex. It supports both Single Data Rate (SDR) and Double Data Rate
(DDR/DDR2/DDR3) SDRAM devices.
The BA317 is an assembly of modules (controller core, user ports and physical interface). According to
the user needs, a top-level can be automatically generated with all modules included.
The controller core includes a multi-port arbiter and a command sequencer. It is optimized to achieve
high bandwidth by mixing accesses to the different banks of the SDRAM. It generates burst of 8 data
with auto-precharge option, allowing continuous data transfer in case of long bursts.
The user port includes FIFO (for both data and addresses). Each port can have a different data bus
width (larger or smaller than the SDRAM bus width). The user port provides access to individual data. It
manages the generation of SDRAM burst.
The physical interface manages the double data rate and the source synchronous data sampling.
Technical Description
General Parameters
Parameter
SDRAM Type
SDRAM width
SDRAM addressing
SDRAM timing
SDRAM operating
parameters
DIMM parameters
Arbitration
Serial Presence Detect
Implementation options
User Port Types
Port type
Buffered
IPIF
Video
Raw
General Parameters
Description
SDR, DDR, DDR2 or DDR3.
Data bus width.
Bank address width; Row address width; Column address width.
These parameters can also be dynamically configured (via SPD).
tRCD; tRP; tRAS; tRC; tWR; tRFC; tREFI; tWTR; tRTP; tFAW.
Clock frequency; CAS latency; CWL Latency; Burst length.
Registered or not; Number of chip select; Number of clock pairs.
Number of ports; number of consecutive read/write accesses.
Included or not.
Possibility to add some pipeline to increase frequency.
Table 1 - General Parameters
Following user ports are available
Description
This is a generic type of port. It includes FIFO, clock domain crossing, data bus
width adaptation, SDRAM burst generation.
The IPIF port allows interfacing with PLB / OPB bus on Xilinx device. The Xilinx
EDK (Embedded Development Kit) provides the modules plb_ipif and opb_ipif as
interface between PLB / OPB and IPIF.
The video ports allow a direct connection to the J2K IP’s of Barco-Silex.
The raw port provides direct access to the controller core. No FIFO is included, no
clock domain crossing is supported, and access is burst based.
Table 2 – User Port Types
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Technical specifications are subject to change without prior notice

User Port Parameters
User port parameters (each port can be individually configured)
Parameter
Description
Port type
Port direction
Data bus
Data mask
Clock
FIFO
Acknowledge
Priority
Buffered, IPIF, Digital Cinema or raw.
Read only, write only or read/write.
Data width is configurable.
It is possible to write single byte using data mask.
Asynchronous or synchronous clock.
FIFO depth is configurable.
Optional acknowledge signal can be generated.
Each port can have high or low priority.
Table 3 – User Port Parameters
SDRAM PHY interfaces
Following PHY interface are available
FPGA
Description
Virtex-4, Virtex-5
Based on IDELAY.
Automatic delay calibration phase at startup.
Virtex-6
Based on Xilinx PHY module
With automatic calibration phase at startup
Spartan-3…
Based on feedback clock.
Stratix-II, Cyclone-II… Based on feedback clock.
Stratix-II
Stratix-III, Stratix-IV, Cyclone-
III, Arria-II GX
Cyclone-III, Cyclone-IV, Stratix-
III, Stratix-IV
Based on Altera legacy datapath.
Based on Altera non-AFI altmemphy module.
With automatic calibration phase at startup.
Based on Altera AFI altmemphy module.
With automatic calibration phase at startup.
Table 4 – SDRAM PHY Interface
Deliverables
● Compiled model available on request for evaluation;
● RTL/VHDL/Synchronous Design;
● TestBench;
● Documentation.
Implementation Data
● The maximum frequency on the physical side depends mainly on the target technology.
● The maximum frequency on user port side depends on the target technology and on the port
parameters.
● The design area varies largely according to the number of ports, the FIFO depth and the data bus
width.
Maturity
● The BA317 has already been used successfully in many projects, using various FPGA.
Signals description
Refer to the datasheet document for a more detailed description.
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Technical specifications are subject to change without prior notice

Barco Silex overview
Barco Silex is a micro-electronic design house located in Belgium and France belonging to the Belgian
Barco group.
Barco Silex offers a complete portfolio of high-end design services, from ASIC/FPGA design to advanced
SoC/SoPC based system development, IP-core design and board design in the fields of:
Image processing
Communications
Consumer electronics
Industrial electronics.
Barco Silex IP products
Barco Silex design expertise is also made available through a wide portfolio of IP products, with a strong
focus on high performance, standardized image processing and encryption functions.
All these IP cores have been designed and fully validated by Barco Silex and are hardware proven,
which guarantees high IP quality as well as best support during your integration phase.
Deliverables include:
RTL Code or netlist (depending on license type)
Functional simulation testbench
Synthesis script
Full documentation
For some of them, we can also provide you with simulation models and a design kit.
These "off the shelf", high quality IP cores provide you with the fastest and most efficient way of
integrating complex functionalities on FPGAs or ASICs, while meeting short time to market constraints.
More information
Order-reference: BA317
For additional information and other IP products contact:
Barco – Silex
e-mail: barco-silex@barco.com
http://www.barco-silex.com
Or contact the local Barco Silex design centers:
Belgium France France
Scientific Park ZI Peynier- Rousset 171b, Av.du Gal De Gaulle
Rue du Bosquet 7 Route de Trets Imm CCE Bat C
1348 Louvain-la Neuve 13790 Peynier 92200 Neuilly sur Seine
+32(0)10/45.49.04 +33 1 47 38 30 89 +33 1 47 38 30 89
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Technical specifications are subject to change without prior notice